Merge branch 'drm-next-4.16' of git://people.freedesktop.org/~agd5f/linux into drm-next

A few fixes for 4.16:
- Cleanup the the remains of ttm io_mem_pfn
- A couple dpm quirks for SI
- Add Chunming as another amdgpu maintainer
- A few more huge page fixes
- A few other misc fixes

* 'drm-next-4.16' of git://people.freedesktop.org/~agd5f/linux:
  drm/amd/pp: Implement get_max_high_clocks for CI/VI
  MAINTAINERS: add David (Chunming) Zhou as additional amdgpu maintainer
  drm/amdgpu: fix 64bit BAR detection
  drm/amdgpu: optimize moved handling only when vm_debug is inactive
  drm/amdgpu: simplify huge page handling
  drm/amdgpu: update VM PDs after the PTs
  drm/amdgpu: minor optimize VM moved handling v2
  drm/amdgpu: loosen the criteria for huge pages a bit
  drm/amd/powerplay: set pp_num_states as 0 on error situation
  drm/ttm: specify DMA_ATTR_NO_WARN for huge page pools
  drm/ttm: remove ttm_bo_default_io_mem_pfn
  staging: remove the default io_mem_pfn set
  drm/amd/powerplay: fix memory leakage when reload (v2)
  drm/amdgpu/gfx9: only init the apertures used by KGD (v2)
  drm/amdgpu: add atpx quirk handling (v2)
  drm/amdgpu: Add dpm quirk for Jet PRO (v2)
  drm/radeon: Add dpm quirk for Jet PRO (v2)

7 files changed, 97 insertions, 63 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
index c13c51af0b68..e2c3c5ec42d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
@@ -14,6 +14,16 @@
 
 #include "amd_acpi.h"
 
+#define AMDGPU_PX_QUIRK_FORCE_ATPX  (1 << 0)
+
+struct amdgpu_px_quirk {
+        u32 chip_vendor;
+        u32 chip_device;
+        u32 subsys_vendor;
+        u32 subsys_device;
+        u32 px_quirk_flags;
+};
+
 struct amdgpu_atpx_functions {
         bool px_params;
         bool power_cntl;
@@ -35,6 +45,7 @@ struct amdgpu_atpx {
 static struct amdgpu_atpx_priv {
         bool atpx_detected;
         bool bridge_pm_usable;
+        unsigned int quirks;
         /* handle for device - and atpx */
         acpi_handle dhandle;
         acpi_handle other_handle;
@@ -205,13 +216,19 @@ static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx)
 
         atpx->is_hybrid = false;
         if (valid_bits & ATPX_MS_HYBRID_GFX_SUPPORTED) {
-                printk("ATPX Hybrid Graphics\n");
-                /*
-                 * Disable legacy PM methods only when pcie port PM is usable,
-                 * otherwise the device might fail to power off or power on.
-                 */
-                atpx->functions.power_cntl = !amdgpu_atpx_priv.bridge_pm_usable;
-                atpx->is_hybrid = true;
+                if (amdgpu_atpx_priv.quirks & AMDGPU_PX_QUIRK_FORCE_ATPX) {
+                        printk("ATPX Hybrid Graphics, forcing to ATPX\n");
+                        atpx->functions.power_cntl = true;
+                        atpx->is_hybrid = false;
+                } else {
+                        printk("ATPX Hybrid Graphics\n");
+                        /*
+                         * Disable legacy PM methods only when pcie port PM is usable,
+                         * otherwise the device might fail to power off or power on.
+                         */
+                        atpx->functions.power_cntl = !amdgpu_atpx_priv.bridge_pm_usable;
+                        atpx->is_hybrid = true;
+                }
         }
 
         atpx->dgpu_req_power_for_displays = false;
@@ -547,6 +564,30 @@ static const struct vga_switcheroo_handler amdgpu_atpx_handler = {
         .get_client_id = amdgpu_atpx_get_client_id,
 };
 
+static const struct amdgpu_px_quirk amdgpu_px_quirk_list[] = {
+        /* HG _PR3 doesn't seem to work on this A+A weston board */
+        { 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX },
+        { 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },
+        { 0, 0, 0, 0, 0 },
+};
+
+static void amdgpu_atpx_get_quirks(struct pci_dev *pdev)
+{
+        const struct amdgpu_px_quirk *p = amdgpu_px_quirk_list;
+
+        /* Apply PX quirks */
+        while (p && p->chip_device != 0) {
+                if (pdev->vendor == p->chip_vendor &&
+                    pdev->device == p->chip_device &&
+                    pdev->subsystem_vendor == p->subsys_vendor &&
+                    pdev->subsystem_device == p->subsys_device) {
+                        amdgpu_atpx_priv.quirks |= p->px_quirk_flags;
+                        break;
+                }
+                ++p;
+        }
+}
+
 /**
  * amdgpu_atpx_detect - detect whether we have PX
  *
@@ -570,6 +611,7 @@ static bool amdgpu_atpx_detect(void)
 
                 parent_pdev = pci_upstream_bridge(pdev);
                 d3_supported |= parent_pdev && parent_pdev->bridge_d3;
+                amdgpu_atpx_get_quirks(pdev);
         }
 
         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
@@ -579,6 +621,7 @@ static bool amdgpu_atpx_detect(void)
 
                 parent_pdev = pci_upstream_bridge(pdev);
                 d3_supported |= parent_pdev && parent_pdev->bridge_d3;
+                amdgpu_atpx_get_quirks(pdev);
         }
 
         if (has_atpx && vga_count == 2) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 5e539fc5b05f..e80fc38141b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -778,10 +778,6 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
         struct amdgpu_bo *bo;
         int i, r;
 
-        r = amdgpu_vm_update_directories(adev, vm);
-        if (r)
-                return r;
-
         r = amdgpu_vm_clear_freed(adev, vm, NULL);
         if (r)
                 return r;
@@ -839,6 +835,10 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
         if (r)
                 return r;
 
+        r = amdgpu_vm_update_directories(adev, vm);
+        if (r)
+                return r;
+
         r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update, false);
         if (r)
                 return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 357cd8bf2e55..9baf182d5418 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -626,7 +626,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
                 root = root->parent;
 
         pci_bus_for_each_resource(root, res, i) {
-                if (res && res->flags & IORESOURCE_MEM_64 &&
+                if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
                     res->start > 0x100000000ull)
                         break;
         }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 10805edcf964..e48b4ec88c8c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -518,10 +518,6 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
         if (!amdgpu_vm_ready(vm))
                 return;
 
-        r = amdgpu_vm_update_directories(adev, vm);
-        if (r)
-                goto error;
-
         r = amdgpu_vm_clear_freed(adev, vm, NULL);
         if (r)
                 goto error;
@@ -530,6 +526,10 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
             operation == AMDGPU_VA_OP_REPLACE)
                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 
+        r = amdgpu_vm_update_directories(adev, vm);
+        if (r)
+                goto error;
+
 error:
         if (r && r != -ERESTARTSYS)
                 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index d4510807a692..cd1752b6afa9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -946,57 +946,38 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
                                         unsigned nptes, uint64_t dst,
                                         uint64_t flags)
 {
-        bool use_cpu_update = (p->func == amdgpu_vm_cpu_set_ptes);
         uint64_t pd_addr, pde;
 
         /* In the case of a mixed PT the PDE must point to it*/
-        if (p->adev->asic_type < CHIP_VEGA10 ||
-            nptes != AMDGPU_VM_PTE_COUNT(p->adev) ||
-            p->src ||
-            !(flags & AMDGPU_PTE_VALID)) {
-
-                dst = amdgpu_bo_gpu_offset(entry->base.bo);
-                flags = AMDGPU_PTE_VALID;
-        } else {
+        if (p->adev->asic_type >= CHIP_VEGA10 && !p->src &&
+            nptes == AMDGPU_VM_PTE_COUNT(p->adev)) {
                 /* Set the huge page flag to stop scanning at this PDE */
                 flags |= AMDGPU_PDE_PTE;
         }
 
-        if (!entry->huge && !(flags & AMDGPU_PDE_PTE))
+        if (!(flags & AMDGPU_PDE_PTE)) {
+                if (entry->huge) {
+                        /* Add the entry to the relocated list to update it. */
+                        entry->huge = false;
+                        spin_lock(&p->vm->status_lock);
+                        list_move(&entry->base.vm_status, &p->vm->relocated);
+                        spin_unlock(&p->vm->status_lock);
+                }
                 return;
-        entry->huge = !!(flags & AMDGPU_PDE_PTE);
+        }
 
+        entry->huge = true;
         amdgpu_gart_get_vm_pde(p->adev, AMDGPU_VM_PDB0,
                                &dst, &flags);
 
-        if (use_cpu_update) {
-                /* In case a huge page is replaced with a system
-                 * memory mapping, p->pages_addr != NULL and
-                 * amdgpu_vm_cpu_set_ptes would try to translate dst
-                 * through amdgpu_vm_map_gart. But dst is already a
-                 * GPU address (of the page table). Disable
-                 * amdgpu_vm_map_gart temporarily.
-                 */
-                dma_addr_t *tmp;
-
-                tmp = p->pages_addr;
-                p->pages_addr = NULL;
-
-                pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo);
-                pde = pd_addr + (entry - parent->entries) * 8;
-                amdgpu_vm_cpu_set_ptes(p, pde, dst, 1, 0, flags);
-
-                p->pages_addr = tmp;
-        } else {
-                if (parent->base.bo->shadow) {
-                        pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow);
-                        pde = pd_addr + (entry - parent->entries) * 8;
-                        amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags);
-                }
-                pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
+        if (parent->base.bo->shadow) {
+                pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow);
                 pde = pd_addr + (entry - parent->entries) * 8;
-                amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags);
+                p->func(p, pde, dst, 1, 0, flags);
         }
+        pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
+        pde = pd_addr + (entry - parent->entries) * 8;
+        p->func(p, pde, dst, 1, 0, flags);
 }
 
 /**
@@ -1208,12 +1189,6 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
         /* padding, etc. */
         ndw = 64;
 
-        /* one PDE write for each huge page */
-        if (vm->root.base.bo->shadow)
-                ndw += ((nptes >> adev->vm_manager.block_size) + 1) * 6 * 2;
-        else
-                ndw += ((nptes >> adev->vm_manager.block_size) + 1) * 6;
-
         if (pages_addr) {
                 /* copy commands needed */
                 ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw;
@@ -1288,8 +1263,6 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 
 error_free:
         amdgpu_job_free(job);
-        amdgpu_vm_invalidate_level(adev, vm, &vm->root,
-                                   adev->vm_manager.root_level);
         return r;
 }
 
@@ -1700,18 +1673,31 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
         spin_lock(&vm->status_lock);
         while (!list_empty(&vm->moved)) {
                 struct amdgpu_bo_va *bo_va;
+                struct reservation_object *resv;
 
                 bo_va = list_first_entry(&vm->moved,
                         struct amdgpu_bo_va, base.vm_status);
                 spin_unlock(&vm->status_lock);
 
+                resv = bo_va->base.bo->tbo.resv;
+
                 /* Per VM BOs never need to bo cleared in the page tables */
-                clear = bo_va->base.bo->tbo.resv != vm->root.base.bo->tbo.resv;
+                if (resv == vm->root.base.bo->tbo.resv)
+                        clear = false;
+                /* Try to reserve the BO to avoid clearing its ptes */
+                else if (!amdgpu_vm_debug && reservation_object_trylock(resv))
+                        clear = false;
+                /* Somebody else is using the BO right now */
+                else
+                        clear = true;
 
                 r = amdgpu_vm_bo_update(adev, bo_va, clear);
                 if (r)
                         return r;
 
+                if (!clear && resv != vm->root.base.bo->tbo.resv)
+                        reservation_object_unlock(resv);
+
                 spin_lock(&vm->status_lock);
         }
         spin_unlock(&vm->status_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 55670dbacace..fc270e2ef91a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1526,7 +1526,7 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
         /* XXX SH_MEM regs */
         /* where to put LDS, scratch, GPUVM in FSA64 space */
         mutex_lock(&adev->srbm_mutex);
-        for (i = 0; i < 16; i++) {
+        for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
                 soc15_grbm_select(adev, 0, 0, 0, i);
                 /* CP and shaders */
                 if (i == 0) {
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 299cb3161b2c..ce675a7f179a 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -3464,6 +3464,11 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
                     (adev->pdev->device == 0x6667)) {
                         max_sclk = 75000;
                 }
+                if ((adev->pdev->revision == 0xC3) ||
+                    (adev->pdev->device == 0x6665)) {
+                        max_sclk = 60000;
+                        max_mclk = 80000;
+                }
         } else if (adev->asic_type == CHIP_OLAND) {
                 if ((adev->pdev->revision == 0xC7) ||
                     (adev->pdev->revision == 0x80) ||