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authorChristian König <christian.koenig@amd.com>2016-03-30 04:50:25 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-05-02 15:26:56 -0400
commit8358dceed981cf389778fba217288da8dadbe103 (patch)
treeb6d333419b958a3ff7eeaa8db2eac6b4304ab318 /drivers/gpu/drm/amd/amdgpu
parentfa3ab3c7babf3c2c8a4a174a532732739a304885 (diff)
drm/amdgpu: use BO pages instead of GART array
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c29
1 files changed, 16 insertions, 13 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 9eec3e1be667..0c92e0450694 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -836,11 +836,12 @@ error_free:
836 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks 836 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
837 * 837 *
838 * @adev: amdgpu_device pointer 838 * @adev: amdgpu_device pointer
839 * @gtt: GART instance to use for mapping 839 * @gtt_flags: flags as they are used for GTT
840 * @pages_addr: DMA addresses to use for mapping
840 * @vm: requested vm 841 * @vm: requested vm
841 * @mapping: mapped range and flags to use for the update 842 * @mapping: mapped range and flags to use for the update
842 * @addr: addr to set the area to 843 * @addr: addr to set the area to
843 * @gtt_flags: flags as they are used for GTT 844 * @flags: HW flags for the mapping
844 * @fence: optional resulting fence 845 * @fence: optional resulting fence
845 * 846 *
846 * Split the mapping into smaller chunks so that each update fits 847 * Split the mapping into smaller chunks so that each update fits
@@ -848,8 +849,8 @@ error_free:
848 * Returns 0 for success, -EINVAL for failure. 849 * Returns 0 for success, -EINVAL for failure.
849 */ 850 */
850static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, 851static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
851 struct amdgpu_gart *gtt,
852 uint32_t gtt_flags, 852 uint32_t gtt_flags,
853 dma_addr_t *pages_addr,
853 struct amdgpu_vm *vm, 854 struct amdgpu_vm *vm,
854 struct amdgpu_bo_va_mapping *mapping, 855 struct amdgpu_bo_va_mapping *mapping,
855 uint32_t flags, uint64_t addr, 856 uint32_t flags, uint64_t addr,
@@ -858,7 +859,6 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
858 const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE; 859 const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE;
859 860
860 uint64_t src = 0, start = mapping->it.start; 861 uint64_t src = 0, start = mapping->it.start;
861 dma_addr_t *pages_addr = NULL;
862 int r; 862 int r;
863 863
864 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here 864 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
@@ -871,16 +871,14 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
871 871
872 trace_amdgpu_vm_bo_update(mapping); 872 trace_amdgpu_vm_bo_update(mapping);
873 873
874 if (gtt) { 874 if (pages_addr) {
875 if (flags == gtt_flags) 875 if (flags == gtt_flags)
876 src = adev->gart.table_addr + (addr >> 12) * 8; 876 src = adev->gart.table_addr + (addr >> 12) * 8;
877 else
878 pages_addr = &gtt->pages_addr[addr >> 12];
879 addr = 0; 877 addr = 0;
880 } 878 }
881 addr += mapping->offset; 879 addr += mapping->offset;
882 880
883 if (!gtt || src) 881 if (!pages_addr || src)
884 return amdgpu_vm_bo_update_mapping(adev, src, pages_addr, vm, 882 return amdgpu_vm_bo_update_mapping(adev, src, pages_addr, vm,
885 start, mapping->it.last, 883 start, mapping->it.last,
886 flags, addr, fence); 884 flags, addr, fence);
@@ -920,16 +918,20 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
920{ 918{
921 struct amdgpu_vm *vm = bo_va->vm; 919 struct amdgpu_vm *vm = bo_va->vm;
922 struct amdgpu_bo_va_mapping *mapping; 920 struct amdgpu_bo_va_mapping *mapping;
923 struct amdgpu_gart *gtt = NULL; 921 dma_addr_t *pages_addr = NULL;
924 uint32_t gtt_flags, flags; 922 uint32_t gtt_flags, flags;
925 uint64_t addr; 923 uint64_t addr;
926 int r; 924 int r;
927 925
928 if (mem) { 926 if (mem) {
927 struct ttm_dma_tt *ttm;
928
929 addr = (u64)mem->start << PAGE_SHIFT; 929 addr = (u64)mem->start << PAGE_SHIFT;
930 switch (mem->mem_type) { 930 switch (mem->mem_type) {
931 case TTM_PL_TT: 931 case TTM_PL_TT:
932 gtt = &bo_va->bo->adev->gart; 932 ttm = container_of(bo_va->bo->tbo.ttm, struct
933 ttm_dma_tt, ttm);
934 pages_addr = ttm->dma_address;
933 break; 935 break;
934 936
935 case TTM_PL_VRAM: 937 case TTM_PL_VRAM:
@@ -952,8 +954,9 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
952 spin_unlock(&vm->status_lock); 954 spin_unlock(&vm->status_lock);
953 955
954 list_for_each_entry(mapping, &bo_va->invalids, list) { 956 list_for_each_entry(mapping, &bo_va->invalids, list) {
955 r = amdgpu_vm_bo_split_mapping(adev, gtt, gtt_flags, vm, mapping, 957 r = amdgpu_vm_bo_split_mapping(adev, gtt_flags, pages_addr, vm,
956 flags, addr, &bo_va->last_pt_update); 958 mapping, flags, addr,
959 &bo_va->last_pt_update);
957 if (r) 960 if (r)
958 return r; 961 return r;
959 } 962 }
@@ -998,7 +1001,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
998 struct amdgpu_bo_va_mapping, list); 1001 struct amdgpu_bo_va_mapping, list);
999 list_del(&mapping->list); 1002 list_del(&mapping->list);
1000 1003
1001 r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, vm, mapping, 1004 r = amdgpu_vm_bo_split_mapping(adev, 0, NULL, vm, mapping,
1002 0, 0, NULL); 1005 0, 0, NULL);
1003 kfree(mapping); 1006 kfree(mapping);
1004 if (r) 1007 if (r)