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authorRex Zhu <Rex.Zhu@amd.com>2018-10-09 06:46:12 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-10-10 15:49:34 -0400
commit800516480652e5ffbd4d7721de1fce484328e158 (patch)
treea5053b8df7b6140656f71379a5c832f074625064 /drivers/gpu/drm/amd/amdgpu
parentb19caa17b5a728845832353337510fcb3cccddf6 (diff)
drm/amdgpu: Remove the direct fw loading support for sdma2.4
sdma2.4 is only for iceland. For Vi, we don't maintain the direct fw loading. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c42
1 files changed, 0 insertions, 42 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index cd781abc4953..2d4770e173dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -504,41 +504,6 @@ static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
504 return 0; 504 return 0;
505} 505}
506 506
507/**
508 * sdma_v2_4_load_microcode - load the sDMA ME ucode
509 *
510 * @adev: amdgpu_device pointer
511 *
512 * Loads the sDMA0/1 ucode.
513 * Returns 0 for success, -EINVAL if the ucode is not available.
514 */
515static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
516{
517 const struct sdma_firmware_header_v1_0 *hdr;
518 const __le32 *fw_data;
519 u32 fw_size;
520 int i, j;
521
522 /* halt the MEs */
523 sdma_v2_4_enable(adev, false);
524
525 for (i = 0; i < adev->sdma.num_instances; i++) {
526 if (!adev->sdma.instance[i].fw)
527 return -EINVAL;
528 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
529 amdgpu_ucode_print_sdma_hdr(&hdr->header);
530 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
531 fw_data = (const __le32 *)
532 (adev->sdma.instance[i].fw->data +
533 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
534 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
535 for (j = 0; j < fw_size; j++)
536 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
537 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
538 }
539
540 return 0;
541}
542 507
543/** 508/**
544 * sdma_v2_4_start - setup and start the async dma engines 509 * sdma_v2_4_start - setup and start the async dma engines
@@ -552,13 +517,6 @@ static int sdma_v2_4_start(struct amdgpu_device *adev)
552{ 517{
553 int r; 518 int r;
554 519
555
556 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
557 r = sdma_v2_4_load_microcode(adev);
558 if (r)
559 return r;
560 }
561
562 /* halt the engine before programing */ 520 /* halt the engine before programing */
563 sdma_v2_4_enable(adev, false); 521 sdma_v2_4_enable(adev, false);
564 522