diff options
author | James Morris <james.morris@microsoft.com> | 2018-03-22 17:26:16 -0400 |
---|---|---|
committer | James Morris <james.morris@microsoft.com> | 2018-03-22 17:26:16 -0400 |
commit | 5893ed18a26d1f56b97c0290b0cbbc2d49d6de28 (patch) | |
tree | 97aa931519fca28a0a12fad7485347198f8267cc /drivers/gpu/drm/amd/amdgpu | |
parent | 7bd698b3c04e61ee9e03d4c2a55003f75df14dca (diff) | |
parent | c698ca5278934c0ae32297a8725ced2e27585d7f (diff) |
Merge tag 'v4.16-rc6' into next-general
Merge to Linux 4.16-rc6 at the request of Jarkko, for his TPM updates.
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
23 files changed, 159 insertions, 161 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index d5a2eefd6c3e..74edba18b159 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h | |||
@@ -1156,7 +1156,7 @@ static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, | |||
1156 | /* | 1156 | /* |
1157 | * Writeback | 1157 | * Writeback |
1158 | */ | 1158 | */ |
1159 | #define AMDGPU_MAX_WB 512 /* Reserve at most 512 WB slots for amdgpu-owned rings. */ | 1159 | #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ |
1160 | 1160 | ||
1161 | struct amdgpu_wb { | 1161 | struct amdgpu_wb { |
1162 | struct amdgpu_bo *wb_obj; | 1162 | struct amdgpu_bo *wb_obj; |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c index 57afad79f55d..8fa850a070e0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | |||
@@ -540,6 +540,9 @@ int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, | |||
540 | size_t size; | 540 | size_t size; |
541 | u32 retry = 3; | 541 | u32 retry = 3; |
542 | 542 | ||
543 | if (amdgpu_acpi_pcie_notify_device_ready(adev)) | ||
544 | return -EINVAL; | ||
545 | |||
543 | /* Get the device handle */ | 546 | /* Get the device handle */ |
544 | handle = ACPI_HANDLE(&adev->pdev->dev); | 547 | handle = ACPI_HANDLE(&adev->pdev->dev); |
545 | if (!handle) | 548 | if (!handle) |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 8ca3783f2deb..7a073ac5f9c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | |||
@@ -69,25 +69,18 @@ void amdgpu_connector_hotplug(struct drm_connector *connector) | |||
69 | /* don't do anything if sink is not display port, i.e., | 69 | /* don't do anything if sink is not display port, i.e., |
70 | * passive dp->(dvi|hdmi) adaptor | 70 | * passive dp->(dvi|hdmi) adaptor |
71 | */ | 71 | */ |
72 | if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { | 72 | if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && |
73 | int saved_dpms = connector->dpms; | 73 | amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && |
74 | /* Only turn off the display if it's physically disconnected */ | 74 | amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { |
75 | if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { | 75 | /* Don't start link training before we have the DPCD */ |
76 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | 76 | if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) |
77 | } else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { | 77 | return; |
78 | /* Don't try to start link training before we | 78 | |
79 | * have the dpcd */ | 79 | /* Turn the connector off and back on immediately, which |
80 | if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) | 80 | * will trigger link training |
81 | return; | 81 | */ |
82 | 82 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
83 | /* set it to OFF so that drm_helper_connector_dpms() | 83 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); |
84 | * won't return immediately since the current state | ||
85 | * is ON at this point. | ||
86 | */ | ||
87 | connector->dpms = DRM_MODE_DPMS_OFF; | ||
88 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | ||
89 | } | ||
90 | connector->dpms = saved_dpms; | ||
91 | } | 84 | } |
92 | } | 85 | } |
93 | } | 86 | } |
@@ -736,9 +729,11 @@ amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) | |||
736 | enum drm_connector_status ret = connector_status_disconnected; | 729 | enum drm_connector_status ret = connector_status_disconnected; |
737 | int r; | 730 | int r; |
738 | 731 | ||
739 | r = pm_runtime_get_sync(connector->dev->dev); | 732 | if (!drm_kms_helper_is_poll_worker()) { |
740 | if (r < 0) | 733 | r = pm_runtime_get_sync(connector->dev->dev); |
741 | return connector_status_disconnected; | 734 | if (r < 0) |
735 | return connector_status_disconnected; | ||
736 | } | ||
742 | 737 | ||
743 | if (encoder) { | 738 | if (encoder) { |
744 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | 739 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); |
@@ -757,8 +752,12 @@ amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) | |||
757 | /* check acpi lid status ??? */ | 752 | /* check acpi lid status ??? */ |
758 | 753 | ||
759 | amdgpu_connector_update_scratch_regs(connector, ret); | 754 | amdgpu_connector_update_scratch_regs(connector, ret); |
760 | pm_runtime_mark_last_busy(connector->dev->dev); | 755 | |
761 | pm_runtime_put_autosuspend(connector->dev->dev); | 756 | if (!drm_kms_helper_is_poll_worker()) { |
757 | pm_runtime_mark_last_busy(connector->dev->dev); | ||
758 | pm_runtime_put_autosuspend(connector->dev->dev); | ||
759 | } | ||
760 | |||
762 | return ret; | 761 | return ret; |
763 | } | 762 | } |
764 | 763 | ||
@@ -868,9 +867,11 @@ amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) | |||
868 | enum drm_connector_status ret = connector_status_disconnected; | 867 | enum drm_connector_status ret = connector_status_disconnected; |
869 | int r; | 868 | int r; |
870 | 869 | ||
871 | r = pm_runtime_get_sync(connector->dev->dev); | 870 | if (!drm_kms_helper_is_poll_worker()) { |
872 | if (r < 0) | 871 | r = pm_runtime_get_sync(connector->dev->dev); |
873 | return connector_status_disconnected; | 872 | if (r < 0) |
873 | return connector_status_disconnected; | ||
874 | } | ||
874 | 875 | ||
875 | encoder = amdgpu_connector_best_single_encoder(connector); | 876 | encoder = amdgpu_connector_best_single_encoder(connector); |
876 | if (!encoder) | 877 | if (!encoder) |
@@ -924,8 +925,10 @@ amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) | |||
924 | amdgpu_connector_update_scratch_regs(connector, ret); | 925 | amdgpu_connector_update_scratch_regs(connector, ret); |
925 | 926 | ||
926 | out: | 927 | out: |
927 | pm_runtime_mark_last_busy(connector->dev->dev); | 928 | if (!drm_kms_helper_is_poll_worker()) { |
928 | pm_runtime_put_autosuspend(connector->dev->dev); | 929 | pm_runtime_mark_last_busy(connector->dev->dev); |
930 | pm_runtime_put_autosuspend(connector->dev->dev); | ||
931 | } | ||
929 | 932 | ||
930 | return ret; | 933 | return ret; |
931 | } | 934 | } |
@@ -988,9 +991,11 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) | |||
988 | enum drm_connector_status ret = connector_status_disconnected; | 991 | enum drm_connector_status ret = connector_status_disconnected; |
989 | bool dret = false, broken_edid = false; | 992 | bool dret = false, broken_edid = false; |
990 | 993 | ||
991 | r = pm_runtime_get_sync(connector->dev->dev); | 994 | if (!drm_kms_helper_is_poll_worker()) { |
992 | if (r < 0) | 995 | r = pm_runtime_get_sync(connector->dev->dev); |
993 | return connector_status_disconnected; | 996 | if (r < 0) |
997 | return connector_status_disconnected; | ||
998 | } | ||
994 | 999 | ||
995 | if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { | 1000 | if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { |
996 | ret = connector->status; | 1001 | ret = connector->status; |
@@ -1115,8 +1120,10 @@ out: | |||
1115 | amdgpu_connector_update_scratch_regs(connector, ret); | 1120 | amdgpu_connector_update_scratch_regs(connector, ret); |
1116 | 1121 | ||
1117 | exit: | 1122 | exit: |
1118 | pm_runtime_mark_last_busy(connector->dev->dev); | 1123 | if (!drm_kms_helper_is_poll_worker()) { |
1119 | pm_runtime_put_autosuspend(connector->dev->dev); | 1124 | pm_runtime_mark_last_busy(connector->dev->dev); |
1125 | pm_runtime_put_autosuspend(connector->dev->dev); | ||
1126 | } | ||
1120 | 1127 | ||
1121 | return ret; | 1128 | return ret; |
1122 | } | 1129 | } |
@@ -1359,9 +1366,11 @@ amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) | |||
1359 | struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); | 1366 | struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); |
1360 | int r; | 1367 | int r; |
1361 | 1368 | ||
1362 | r = pm_runtime_get_sync(connector->dev->dev); | 1369 | if (!drm_kms_helper_is_poll_worker()) { |
1363 | if (r < 0) | 1370 | r = pm_runtime_get_sync(connector->dev->dev); |
1364 | return connector_status_disconnected; | 1371 | if (r < 0) |
1372 | return connector_status_disconnected; | ||
1373 | } | ||
1365 | 1374 | ||
1366 | if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { | 1375 | if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { |
1367 | ret = connector->status; | 1376 | ret = connector->status; |
@@ -1429,8 +1438,10 @@ amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) | |||
1429 | 1438 | ||
1430 | amdgpu_connector_update_scratch_regs(connector, ret); | 1439 | amdgpu_connector_update_scratch_regs(connector, ret); |
1431 | out: | 1440 | out: |
1432 | pm_runtime_mark_last_busy(connector->dev->dev); | 1441 | if (!drm_kms_helper_is_poll_worker()) { |
1433 | pm_runtime_put_autosuspend(connector->dev->dev); | 1442 | pm_runtime_mark_last_busy(connector->dev->dev); |
1443 | pm_runtime_put_autosuspend(connector->dev->dev); | ||
1444 | } | ||
1434 | 1445 | ||
1435 | return ret; | 1446 | return ret; |
1436 | } | 1447 | } |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 00a50cc5ec9a..af1b879a9ee9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | |||
@@ -492,7 +492,7 @@ static int amdgpu_device_wb_init(struct amdgpu_device *adev) | |||
492 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | 492 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); |
493 | 493 | ||
494 | /* clear wb memory */ | 494 | /* clear wb memory */ |
495 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t)); | 495 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8); |
496 | } | 496 | } |
497 | 497 | ||
498 | return 0; | 498 | return 0; |
@@ -530,8 +530,9 @@ int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) | |||
530 | */ | 530 | */ |
531 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) | 531 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) |
532 | { | 532 | { |
533 | wb >>= 3; | ||
533 | if (wb < adev->wb.num_wb) | 534 | if (wb < adev->wb.num_wb) |
534 | __clear_bit(wb >> 3, adev->wb.used); | 535 | __clear_bit(wb, adev->wb.used); |
535 | } | 536 | } |
536 | 537 | ||
537 | /** | 538 | /** |
@@ -1455,11 +1456,6 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev) | |||
1455 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | 1456 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
1456 | if (!adev->ip_blocks[i].status.hw) | 1457 | if (!adev->ip_blocks[i].status.hw) |
1457 | continue; | 1458 | continue; |
1458 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | ||
1459 | amdgpu_free_static_csa(adev); | ||
1460 | amdgpu_device_wb_fini(adev); | ||
1461 | amdgpu_device_vram_scratch_fini(adev); | ||
1462 | } | ||
1463 | 1459 | ||
1464 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | 1460 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
1465 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | 1461 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { |
@@ -1486,6 +1482,13 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev) | |||
1486 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | 1482 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
1487 | if (!adev->ip_blocks[i].status.sw) | 1483 | if (!adev->ip_blocks[i].status.sw) |
1488 | continue; | 1484 | continue; |
1485 | |||
1486 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | ||
1487 | amdgpu_free_static_csa(adev); | ||
1488 | amdgpu_device_wb_fini(adev); | ||
1489 | amdgpu_device_vram_scratch_fini(adev); | ||
1490 | } | ||
1491 | |||
1489 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); | 1492 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
1490 | /* XXX handle errors */ | 1493 | /* XXX handle errors */ |
1491 | if (r) { | 1494 | if (r) { |
@@ -2284,14 +2287,6 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) | |||
2284 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | 2287 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); |
2285 | } | 2288 | } |
2286 | drm_modeset_unlock_all(dev); | 2289 | drm_modeset_unlock_all(dev); |
2287 | } else { | ||
2288 | /* | ||
2289 | * There is no equivalent atomic helper to turn on | ||
2290 | * display, so we defined our own function for this, | ||
2291 | * once suspend resume is supported by the atomic | ||
2292 | * framework this will be reworked | ||
2293 | */ | ||
2294 | amdgpu_dm_display_resume(adev); | ||
2295 | } | 2290 | } |
2296 | } | 2291 | } |
2297 | 2292 | ||
@@ -2726,7 +2721,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, | |||
2726 | if (amdgpu_device_has_dc_support(adev)) { | 2721 | if (amdgpu_device_has_dc_support(adev)) { |
2727 | if (drm_atomic_helper_resume(adev->ddev, state)) | 2722 | if (drm_atomic_helper_resume(adev->ddev, state)) |
2728 | dev_info(adev->dev, "drm resume failed:%d\n", r); | 2723 | dev_info(adev->dev, "drm resume failed:%d\n", r); |
2729 | amdgpu_dm_display_resume(adev); | ||
2730 | } else { | 2724 | } else { |
2731 | drm_helper_resume_force_mode(adev->ddev); | 2725 | drm_helper_resume_force_mode(adev->ddev); |
2732 | } | 2726 | } |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index e48b4ec88c8c..ca6c931dabfa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | |||
@@ -36,8 +36,6 @@ void amdgpu_gem_object_free(struct drm_gem_object *gobj) | |||
36 | struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); | 36 | struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); |
37 | 37 | ||
38 | if (robj) { | 38 | if (robj) { |
39 | if (robj->gem_base.import_attach) | ||
40 | drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg); | ||
41 | amdgpu_mn_unregister(robj); | 39 | amdgpu_mn_unregister(robj); |
42 | amdgpu_bo_unref(&robj); | 40 | amdgpu_bo_unref(&robj); |
43 | } | 41 | } |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index e14ab34d8262..7c2be32c5aea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | |||
@@ -75,7 +75,7 @@ static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager *man, | |||
75 | static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man) | 75 | static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man) |
76 | { | 76 | { |
77 | struct amdgpu_gtt_mgr *mgr = man->priv; | 77 | struct amdgpu_gtt_mgr *mgr = man->priv; |
78 | 78 | spin_lock(&mgr->lock); | |
79 | drm_mm_takedown(&mgr->mm); | 79 | drm_mm_takedown(&mgr->mm); |
80 | spin_unlock(&mgr->lock); | 80 | spin_unlock(&mgr->lock); |
81 | kfree(mgr); | 81 | kfree(mgr); |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 56bcd59c3399..36483e0d3c97 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | |||
@@ -257,7 +257,8 @@ int amdgpu_irq_init(struct amdgpu_device *adev) | |||
257 | r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq); | 257 | r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq); |
258 | if (r) { | 258 | if (r) { |
259 | adev->irq.installed = false; | 259 | adev->irq.installed = false; |
260 | flush_work(&adev->hotplug_work); | 260 | if (!amdgpu_device_has_dc_support(adev)) |
261 | flush_work(&adev->hotplug_work); | ||
261 | cancel_work_sync(&adev->reset_work); | 262 | cancel_work_sync(&adev->reset_work); |
262 | return r; | 263 | return r; |
263 | } | 264 | } |
@@ -282,7 +283,8 @@ void amdgpu_irq_fini(struct amdgpu_device *adev) | |||
282 | adev->irq.installed = false; | 283 | adev->irq.installed = false; |
283 | if (adev->irq.msi_enabled) | 284 | if (adev->irq.msi_enabled) |
284 | pci_disable_msi(adev->pdev); | 285 | pci_disable_msi(adev->pdev); |
285 | flush_work(&adev->hotplug_work); | 286 | if (!amdgpu_device_has_dc_support(adev)) |
287 | flush_work(&adev->hotplug_work); | ||
286 | cancel_work_sync(&adev->reset_work); | 288 | cancel_work_sync(&adev->reset_work); |
287 | } | 289 | } |
288 | 290 | ||
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 54f06c959340..2264c5c97009 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | |||
@@ -352,6 +352,7 @@ struct amdgpu_mode_info { | |||
352 | u16 firmware_flags; | 352 | u16 firmware_flags; |
353 | /* pointer to backlight encoder */ | 353 | /* pointer to backlight encoder */ |
354 | struct amdgpu_encoder *bl_encoder; | 354 | struct amdgpu_encoder *bl_encoder; |
355 | u8 bl_level; /* saved backlight level */ | ||
355 | struct amdgpu_audio audio; /* audio stuff */ | 356 | struct amdgpu_audio audio; /* audio stuff */ |
356 | int num_crtc; /* number of crtcs */ | 357 | int num_crtc; /* number of crtcs */ |
357 | int num_hpd; /* number of hpd pins */ | 358 | int num_hpd; /* number of hpd pins */ |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 5c4c3e0d527b..1220322c1680 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | |||
@@ -56,6 +56,8 @@ static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo) | |||
56 | 56 | ||
57 | amdgpu_bo_kunmap(bo); | 57 | amdgpu_bo_kunmap(bo); |
58 | 58 | ||
59 | if (bo->gem_base.import_attach) | ||
60 | drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg); | ||
59 | drm_gem_object_release(&bo->gem_base); | 61 | drm_gem_object_release(&bo->gem_base); |
60 | amdgpu_bo_unref(&bo->parent); | 62 | amdgpu_bo_unref(&bo->parent); |
61 | if (!list_empty(&bo->shadow_list)) { | 63 | if (!list_empty(&bo->shadow_list)) { |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 13044e66dcaf..561d3312af32 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | |||
@@ -481,7 +481,7 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, | |||
481 | result = 0; | 481 | result = 0; |
482 | 482 | ||
483 | if (*pos < 12) { | 483 | if (*pos < 12) { |
484 | early[0] = amdgpu_ring_get_rptr(ring); | 484 | early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask; |
485 | early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; | 485 | early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; |
486 | early[2] = ring->wptr & ring->buf_mask; | 486 | early[2] = ring->wptr & ring->buf_mask; |
487 | for (i = *pos / 4; i < 3 && size; i++) { | 487 | for (i = *pos / 4; i < 3 && size; i++) { |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index b2eae86bf906..5c26a8e806b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | |||
@@ -299,12 +299,15 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev) | |||
299 | 299 | ||
300 | cancel_delayed_work_sync(&adev->uvd.idle_work); | 300 | cancel_delayed_work_sync(&adev->uvd.idle_work); |
301 | 301 | ||
302 | for (i = 0; i < adev->uvd.max_handles; ++i) | 302 | /* only valid for physical mode */ |
303 | if (atomic_read(&adev->uvd.handles[i])) | 303 | if (adev->asic_type < CHIP_POLARIS10) { |
304 | break; | 304 | for (i = 0; i < adev->uvd.max_handles; ++i) |
305 | if (atomic_read(&adev->uvd.handles[i])) | ||
306 | break; | ||
305 | 307 | ||
306 | if (i == AMDGPU_MAX_UVD_HANDLES) | 308 | if (i == adev->uvd.max_handles) |
307 | return 0; | 309 | return 0; |
310 | } | ||
308 | 311 | ||
309 | size = amdgpu_bo_size(adev->uvd.vcpu_bo); | 312 | size = amdgpu_bo_size(adev->uvd.vcpu_bo); |
310 | ptr = adev->uvd.cpu_addr; | 313 | ptr = adev->uvd.cpu_addr; |
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index 2af26d2da127..d702fb8e3427 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | |||
@@ -34,7 +34,7 @@ | |||
34 | #include <linux/backlight.h> | 34 | #include <linux/backlight.h> |
35 | #include "bif/bif_4_1_d.h" | 35 | #include "bif/bif_4_1_d.h" |
36 | 36 | ||
37 | static u8 | 37 | u8 |
38 | amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev) | 38 | amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev) |
39 | { | 39 | { |
40 | u8 backlight_level; | 40 | u8 backlight_level; |
@@ -48,7 +48,7 @@ amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev) | |||
48 | return backlight_level; | 48 | return backlight_level; |
49 | } | 49 | } |
50 | 50 | ||
51 | static void | 51 | void |
52 | amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device *adev, | 52 | amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device *adev, |
53 | u8 backlight_level) | 53 | u8 backlight_level) |
54 | { | 54 | { |
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h index 2bdec40515ce..f77cbdef679e 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h | |||
@@ -25,6 +25,11 @@ | |||
25 | #define __ATOMBIOS_ENCODER_H__ | 25 | #define __ATOMBIOS_ENCODER_H__ |
26 | 26 | ||
27 | u8 | 27 | u8 |
28 | amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev); | ||
29 | void | ||
30 | amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device *adev, | ||
31 | u8 backlight_level); | ||
32 | u8 | ||
28 | amdgpu_atombios_encoder_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder); | 33 | amdgpu_atombios_encoder_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder); |
29 | void | 34 | void |
30 | amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder, | 35 | amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder, |
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index f34bc68aadfb..022f303463fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | |||
@@ -2921,6 +2921,11 @@ static int dce_v10_0_hw_fini(void *handle) | |||
2921 | 2921 | ||
2922 | static int dce_v10_0_suspend(void *handle) | 2922 | static int dce_v10_0_suspend(void *handle) |
2923 | { | 2923 | { |
2924 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | ||
2925 | |||
2926 | adev->mode_info.bl_level = | ||
2927 | amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); | ||
2928 | |||
2924 | return dce_v10_0_hw_fini(handle); | 2929 | return dce_v10_0_hw_fini(handle); |
2925 | } | 2930 | } |
2926 | 2931 | ||
@@ -2929,6 +2934,9 @@ static int dce_v10_0_resume(void *handle) | |||
2929 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | 2934 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
2930 | int ret; | 2935 | int ret; |
2931 | 2936 | ||
2937 | amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, | ||
2938 | adev->mode_info.bl_level); | ||
2939 | |||
2932 | ret = dce_v10_0_hw_init(handle); | 2940 | ret = dce_v10_0_hw_init(handle); |
2933 | 2941 | ||
2934 | /* turn on the BL */ | 2942 | /* turn on the BL */ |
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 26378bd6aba4..800a9f36ab4f 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | |||
@@ -3047,6 +3047,11 @@ static int dce_v11_0_hw_fini(void *handle) | |||
3047 | 3047 | ||
3048 | static int dce_v11_0_suspend(void *handle) | 3048 | static int dce_v11_0_suspend(void *handle) |
3049 | { | 3049 | { |
3050 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | ||
3051 | |||
3052 | adev->mode_info.bl_level = | ||
3053 | amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); | ||
3054 | |||
3050 | return dce_v11_0_hw_fini(handle); | 3055 | return dce_v11_0_hw_fini(handle); |
3051 | } | 3056 | } |
3052 | 3057 | ||
@@ -3055,6 +3060,9 @@ static int dce_v11_0_resume(void *handle) | |||
3055 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | 3060 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
3056 | int ret; | 3061 | int ret; |
3057 | 3062 | ||
3063 | amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, | ||
3064 | adev->mode_info.bl_level); | ||
3065 | |||
3058 | ret = dce_v11_0_hw_init(handle); | 3066 | ret = dce_v11_0_hw_init(handle); |
3059 | 3067 | ||
3060 | /* turn on the BL */ | 3068 | /* turn on the BL */ |
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index bd2c4f727df6..b8368f69ce1f 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | |||
@@ -2787,6 +2787,11 @@ static int dce_v6_0_hw_fini(void *handle) | |||
2787 | 2787 | ||
2788 | static int dce_v6_0_suspend(void *handle) | 2788 | static int dce_v6_0_suspend(void *handle) |
2789 | { | 2789 | { |
2790 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | ||
2791 | |||
2792 | adev->mode_info.bl_level = | ||
2793 | amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); | ||
2794 | |||
2790 | return dce_v6_0_hw_fini(handle); | 2795 | return dce_v6_0_hw_fini(handle); |
2791 | } | 2796 | } |
2792 | 2797 | ||
@@ -2795,6 +2800,9 @@ static int dce_v6_0_resume(void *handle) | |||
2795 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | 2800 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
2796 | int ret; | 2801 | int ret; |
2797 | 2802 | ||
2803 | amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, | ||
2804 | adev->mode_info.bl_level); | ||
2805 | |||
2798 | ret = dce_v6_0_hw_init(handle); | 2806 | ret = dce_v6_0_hw_init(handle); |
2799 | 2807 | ||
2800 | /* turn on the BL */ | 2808 | /* turn on the BL */ |
@@ -3093,7 +3101,7 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev, | |||
3093 | tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; | 3101 | tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; |
3094 | WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); | 3102 | WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); |
3095 | schedule_work(&adev->hotplug_work); | 3103 | schedule_work(&adev->hotplug_work); |
3096 | DRM_INFO("IH: HPD%d\n", hpd + 1); | 3104 | DRM_DEBUG("IH: HPD%d\n", hpd + 1); |
3097 | } | 3105 | } |
3098 | 3106 | ||
3099 | return 0; | 3107 | return 0; |
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index c008dc030687..012e0a9ae0ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | |||
@@ -2819,6 +2819,11 @@ static int dce_v8_0_hw_fini(void *handle) | |||
2819 | 2819 | ||
2820 | static int dce_v8_0_suspend(void *handle) | 2820 | static int dce_v8_0_suspend(void *handle) |
2821 | { | 2821 | { |
2822 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | ||
2823 | |||
2824 | adev->mode_info.bl_level = | ||
2825 | amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); | ||
2826 | |||
2822 | return dce_v8_0_hw_fini(handle); | 2827 | return dce_v8_0_hw_fini(handle); |
2823 | } | 2828 | } |
2824 | 2829 | ||
@@ -2827,6 +2832,9 @@ static int dce_v8_0_resume(void *handle) | |||
2827 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | 2832 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
2828 | int ret; | 2833 | int ret; |
2829 | 2834 | ||
2835 | amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, | ||
2836 | adev->mode_info.bl_level); | ||
2837 | |||
2830 | ret = dce_v8_0_hw_init(handle); | 2838 | ret = dce_v8_0_hw_init(handle); |
2831 | 2839 | ||
2832 | /* turn on the BL */ | 2840 | /* turn on the BL */ |
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index a066c5eda135..a4309698e76c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | |||
@@ -4384,34 +4384,8 @@ static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev) | |||
4384 | case CHIP_KAVERI: | 4384 | case CHIP_KAVERI: |
4385 | adev->gfx.config.max_shader_engines = 1; | 4385 | adev->gfx.config.max_shader_engines = 1; |
4386 | adev->gfx.config.max_tile_pipes = 4; | 4386 | adev->gfx.config.max_tile_pipes = 4; |
4387 | if ((adev->pdev->device == 0x1304) || | 4387 | adev->gfx.config.max_cu_per_sh = 8; |
4388 | (adev->pdev->device == 0x1305) || | 4388 | adev->gfx.config.max_backends_per_se = 2; |
4389 | (adev->pdev->device == 0x130C) || | ||
4390 | (adev->pdev->device == 0x130F) || | ||
4391 | (adev->pdev->device == 0x1310) || | ||
4392 | (adev->pdev->device == 0x1311) || | ||
4393 | (adev->pdev->device == 0x131C)) { | ||
4394 | adev->gfx.config.max_cu_per_sh = 8; | ||
4395 | adev->gfx.config.max_backends_per_se = 2; | ||
4396 | } else if ((adev->pdev->device == 0x1309) || | ||
4397 | (adev->pdev->device == 0x130A) || | ||
4398 | (adev->pdev->device == 0x130D) || | ||
4399 | (adev->pdev->device == 0x1313) || | ||
4400 | (adev->pdev->device == 0x131D)) { | ||
4401 | adev->gfx.config.max_cu_per_sh = 6; | ||
4402 | adev->gfx.config.max_backends_per_se = 2; | ||
4403 | } else if ((adev->pdev->device == 0x1306) || | ||
4404 | (adev->pdev->device == 0x1307) || | ||
4405 | (adev->pdev->device == 0x130B) || | ||
4406 | (adev->pdev->device == 0x130E) || | ||
4407 | (adev->pdev->device == 0x1315) || | ||
4408 | (adev->pdev->device == 0x131B)) { | ||
4409 | adev->gfx.config.max_cu_per_sh = 4; | ||
4410 | adev->gfx.config.max_backends_per_se = 1; | ||
4411 | } else { | ||
4412 | adev->gfx.config.max_cu_per_sh = 3; | ||
4413 | adev->gfx.config.max_backends_per_se = 1; | ||
4414 | } | ||
4415 | adev->gfx.config.max_sh_per_se = 1; | 4389 | adev->gfx.config.max_sh_per_se = 1; |
4416 | adev->gfx.config.max_texture_channel_caches = 4; | 4390 | adev->gfx.config.max_texture_channel_caches = 4; |
4417 | adev->gfx.config.max_gprs = 256; | 4391 | adev->gfx.config.max_gprs = 256; |
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 2719937e09d6..3b7e7af09ead 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | |||
@@ -634,7 +634,7 @@ static int gmc_v9_0_late_init(void *handle) | |||
634 | for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i) | 634 | for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i) |
635 | BUG_ON(vm_inv_eng[i] > 16); | 635 | BUG_ON(vm_inv_eng[i] > 16); |
636 | 636 | ||
637 | if (adev->asic_type == CHIP_VEGA10) { | 637 | if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) { |
638 | r = gmc_v9_0_ecc_available(adev); | 638 | r = gmc_v9_0_ecc_available(adev); |
639 | if (r == 1) { | 639 | if (r == 1) { |
640 | DRM_INFO("ECC is active.\n"); | 640 | DRM_INFO("ECC is active.\n"); |
@@ -682,7 +682,10 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) | |||
682 | adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); | 682 | adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); |
683 | if (!adev->mc.vram_width) { | 683 | if (!adev->mc.vram_width) { |
684 | /* hbm memory channel size */ | 684 | /* hbm memory channel size */ |
685 | chansize = 128; | 685 | if (adev->flags & AMD_IS_APU) |
686 | chansize = 64; | ||
687 | else | ||
688 | chansize = 128; | ||
686 | 689 | ||
687 | tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); | 690 | tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); |
688 | tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK; | 691 | tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK; |
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index e92fb372bc99..91cf95a8c39c 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | |||
@@ -238,31 +238,27 @@ static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) | |||
238 | static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) | 238 | static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) |
239 | { | 239 | { |
240 | struct amdgpu_device *adev = ring->adev; | 240 | struct amdgpu_device *adev = ring->adev; |
241 | u64 *wptr = NULL; | 241 | u64 wptr; |
242 | uint64_t local_wptr = 0; | ||
243 | 242 | ||
244 | if (ring->use_doorbell) { | 243 | if (ring->use_doorbell) { |
245 | /* XXX check if swapping is necessary on BE */ | 244 | /* XXX check if swapping is necessary on BE */ |
246 | wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]); | 245 | wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); |
247 | DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr); | 246 | DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); |
248 | *wptr = (*wptr) >> 2; | ||
249 | DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr); | ||
250 | } else { | 247 | } else { |
251 | u32 lowbit, highbit; | 248 | u32 lowbit, highbit; |
252 | int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; | 249 | int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; |
253 | 250 | ||
254 | wptr = &local_wptr; | ||
255 | lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR)) >> 2; | 251 | lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR)) >> 2; |
256 | highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; | 252 | highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; |
257 | 253 | ||
258 | DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n", | 254 | DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n", |
259 | me, highbit, lowbit); | 255 | me, highbit, lowbit); |
260 | *wptr = highbit; | 256 | wptr = highbit; |
261 | *wptr = (*wptr) << 32; | 257 | wptr = wptr << 32; |
262 | *wptr |= lowbit; | 258 | wptr |= lowbit; |
263 | } | 259 | } |
264 | 260 | ||
265 | return *wptr; | 261 | return wptr >> 2; |
266 | } | 262 | } |
267 | 263 | ||
268 | /** | 264 | /** |
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 543101d5a5ed..2095173aaabf 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c | |||
@@ -31,6 +31,7 @@ | |||
31 | #include "amdgpu_uvd.h" | 31 | #include "amdgpu_uvd.h" |
32 | #include "amdgpu_vce.h" | 32 | #include "amdgpu_vce.h" |
33 | #include "atom.h" | 33 | #include "atom.h" |
34 | #include "amd_pcie.h" | ||
34 | #include "amdgpu_powerplay.h" | 35 | #include "amdgpu_powerplay.h" |
35 | #include "sid.h" | 36 | #include "sid.h" |
36 | #include "si_ih.h" | 37 | #include "si_ih.h" |
@@ -1461,8 +1462,8 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) | |||
1461 | { | 1462 | { |
1462 | struct pci_dev *root = adev->pdev->bus->self; | 1463 | struct pci_dev *root = adev->pdev->bus->self; |
1463 | int bridge_pos, gpu_pos; | 1464 | int bridge_pos, gpu_pos; |
1464 | u32 speed_cntl, mask, current_data_rate; | 1465 | u32 speed_cntl, current_data_rate; |
1465 | int ret, i; | 1466 | int i; |
1466 | u16 tmp16; | 1467 | u16 tmp16; |
1467 | 1468 | ||
1468 | if (pci_is_root_bus(adev->pdev->bus)) | 1469 | if (pci_is_root_bus(adev->pdev->bus)) |
@@ -1474,23 +1475,20 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) | |||
1474 | if (adev->flags & AMD_IS_APU) | 1475 | if (adev->flags & AMD_IS_APU) |
1475 | return; | 1476 | return; |
1476 | 1477 | ||
1477 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | 1478 | if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | |
1478 | if (ret != 0) | 1479 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) |
1479 | return; | ||
1480 | |||
1481 | if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80))) | ||
1482 | return; | 1480 | return; |
1483 | 1481 | ||
1484 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); | 1482 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
1485 | current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >> | 1483 | current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >> |
1486 | LC_CURRENT_DATA_RATE_SHIFT; | 1484 | LC_CURRENT_DATA_RATE_SHIFT; |
1487 | if (mask & DRM_PCIE_SPEED_80) { | 1485 | if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { |
1488 | if (current_data_rate == 2) { | 1486 | if (current_data_rate == 2) { |
1489 | DRM_INFO("PCIE gen 3 link speeds already enabled\n"); | 1487 | DRM_INFO("PCIE gen 3 link speeds already enabled\n"); |
1490 | return; | 1488 | return; |
1491 | } | 1489 | } |
1492 | DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"); | 1490 | DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"); |
1493 | } else if (mask & DRM_PCIE_SPEED_50) { | 1491 | } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) { |
1494 | if (current_data_rate == 1) { | 1492 | if (current_data_rate == 1) { |
1495 | DRM_INFO("PCIE gen 2 link speeds already enabled\n"); | 1493 | DRM_INFO("PCIE gen 2 link speeds already enabled\n"); |
1496 | return; | 1494 | return; |
@@ -1506,7 +1504,7 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) | |||
1506 | if (!gpu_pos) | 1504 | if (!gpu_pos) |
1507 | return; | 1505 | return; |
1508 | 1506 | ||
1509 | if (mask & DRM_PCIE_SPEED_80) { | 1507 | if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { |
1510 | if (current_data_rate != 2) { | 1508 | if (current_data_rate != 2) { |
1511 | u16 bridge_cfg, gpu_cfg; | 1509 | u16 bridge_cfg, gpu_cfg; |
1512 | u16 bridge_cfg2, gpu_cfg2; | 1510 | u16 bridge_cfg2, gpu_cfg2; |
@@ -1589,9 +1587,9 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) | |||
1589 | 1587 | ||
1590 | pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); | 1588 | pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); |
1591 | tmp16 &= ~0xf; | 1589 | tmp16 &= ~0xf; |
1592 | if (mask & DRM_PCIE_SPEED_80) | 1590 | if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) |
1593 | tmp16 |= 3; | 1591 | tmp16 |= 3; |
1594 | else if (mask & DRM_PCIE_SPEED_50) | 1592 | else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) |
1595 | tmp16 |= 2; | 1593 | tmp16 |= 2; |
1596 | else | 1594 | else |
1597 | tmp16 |= 1; | 1595 | tmp16 |= 1; |
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c index ce675a7f179a..22f0b7ff3ac9 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include "amdgpu_pm.h" | 26 | #include "amdgpu_pm.h" |
27 | #include "amdgpu_dpm.h" | 27 | #include "amdgpu_dpm.h" |
28 | #include "amdgpu_atombios.h" | 28 | #include "amdgpu_atombios.h" |
29 | #include "amd_pcie.h" | ||
29 | #include "sid.h" | 30 | #include "sid.h" |
30 | #include "r600_dpm.h" | 31 | #include "r600_dpm.h" |
31 | #include "si_dpm.h" | 32 | #include "si_dpm.h" |
@@ -3331,29 +3332,6 @@ static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev, | |||
3331 | } | 3332 | } |
3332 | } | 3333 | } |
3333 | 3334 | ||
3334 | static enum amdgpu_pcie_gen r600_get_pcie_gen_support(struct amdgpu_device *adev, | ||
3335 | u32 sys_mask, | ||
3336 | enum amdgpu_pcie_gen asic_gen, | ||
3337 | enum amdgpu_pcie_gen default_gen) | ||
3338 | { | ||
3339 | switch (asic_gen) { | ||
3340 | case AMDGPU_PCIE_GEN1: | ||
3341 | return AMDGPU_PCIE_GEN1; | ||
3342 | case AMDGPU_PCIE_GEN2: | ||
3343 | return AMDGPU_PCIE_GEN2; | ||
3344 | case AMDGPU_PCIE_GEN3: | ||
3345 | return AMDGPU_PCIE_GEN3; | ||
3346 | default: | ||
3347 | if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3)) | ||
3348 | return AMDGPU_PCIE_GEN3; | ||
3349 | else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2)) | ||
3350 | return AMDGPU_PCIE_GEN2; | ||
3351 | else | ||
3352 | return AMDGPU_PCIE_GEN1; | ||
3353 | } | ||
3354 | return AMDGPU_PCIE_GEN1; | ||
3355 | } | ||
3356 | |||
3357 | static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, | 3335 | static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, |
3358 | u32 *p, u32 *u) | 3336 | u32 *p, u32 *u) |
3359 | { | 3337 | { |
@@ -5028,10 +5006,11 @@ static int si_populate_smc_acpi_state(struct amdgpu_device *adev, | |||
5028 | table->ACPIState.levels[0].vddc.index, | 5006 | table->ACPIState.levels[0].vddc.index, |
5029 | &table->ACPIState.levels[0].std_vddc); | 5007 | &table->ACPIState.levels[0].std_vddc); |
5030 | } | 5008 | } |
5031 | table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(adev, | 5009 | table->ACPIState.levels[0].gen2PCIE = |
5032 | si_pi->sys_pcie_mask, | 5010 | (u8)amdgpu_get_pcie_gen_support(adev, |
5033 | si_pi->boot_pcie_gen, | 5011 | si_pi->sys_pcie_mask, |
5034 | AMDGPU_PCIE_GEN1); | 5012 | si_pi->boot_pcie_gen, |
5013 | AMDGPU_PCIE_GEN1); | ||
5035 | 5014 | ||
5036 | if (si_pi->vddc_phase_shed_control) | 5015 | if (si_pi->vddc_phase_shed_control) |
5037 | si_populate_phase_shedding_value(adev, | 5016 | si_populate_phase_shedding_value(adev, |
@@ -7168,10 +7147,10 @@ static void si_parse_pplib_clock_info(struct amdgpu_device *adev, | |||
7168 | pl->vddc = le16_to_cpu(clock_info->si.usVDDC); | 7147 | pl->vddc = le16_to_cpu(clock_info->si.usVDDC); |
7169 | pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); | 7148 | pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); |
7170 | pl->flags = le32_to_cpu(clock_info->si.ulFlags); | 7149 | pl->flags = le32_to_cpu(clock_info->si.ulFlags); |
7171 | pl->pcie_gen = r600_get_pcie_gen_support(adev, | 7150 | pl->pcie_gen = amdgpu_get_pcie_gen_support(adev, |
7172 | si_pi->sys_pcie_mask, | 7151 | si_pi->sys_pcie_mask, |
7173 | si_pi->boot_pcie_gen, | 7152 | si_pi->boot_pcie_gen, |
7174 | clock_info->si.ucPCIEGen); | 7153 | clock_info->si.ucPCIEGen); |
7175 | 7154 | ||
7176 | /* patch up vddc if necessary */ | 7155 | /* patch up vddc if necessary */ |
7177 | ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc, | 7156 | ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc, |
@@ -7326,7 +7305,6 @@ static int si_dpm_init(struct amdgpu_device *adev) | |||
7326 | struct si_power_info *si_pi; | 7305 | struct si_power_info *si_pi; |
7327 | struct atom_clock_dividers dividers; | 7306 | struct atom_clock_dividers dividers; |
7328 | int ret; | 7307 | int ret; |
7329 | u32 mask; | ||
7330 | 7308 | ||
7331 | si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); | 7309 | si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); |
7332 | if (si_pi == NULL) | 7310 | if (si_pi == NULL) |
@@ -7336,11 +7314,9 @@ static int si_dpm_init(struct amdgpu_device *adev) | |||
7336 | eg_pi = &ni_pi->eg; | 7314 | eg_pi = &ni_pi->eg; |
7337 | pi = &eg_pi->rv7xx; | 7315 | pi = &eg_pi->rv7xx; |
7338 | 7316 | ||
7339 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | 7317 | si_pi->sys_pcie_mask = |
7340 | if (ret) | 7318 | (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >> |
7341 | si_pi->sys_pcie_mask = 0; | 7319 | CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT; |
7342 | else | ||
7343 | si_pi->sys_pcie_mask = mask; | ||
7344 | si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID; | 7320 | si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID; |
7345 | si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev); | 7321 | si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev); |
7346 | 7322 | ||
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index b2bfedaf57f1..9bab4842cd44 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | |||
@@ -1618,7 +1618,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = { | |||
1618 | .set_wptr = uvd_v6_0_enc_ring_set_wptr, | 1618 | .set_wptr = uvd_v6_0_enc_ring_set_wptr, |
1619 | .emit_frame_size = | 1619 | .emit_frame_size = |
1620 | 4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */ | 1620 | 4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */ |
1621 | 6 + /* uvd_v6_0_enc_ring_emit_vm_flush */ | 1621 | 5 + /* uvd_v6_0_enc_ring_emit_vm_flush */ |
1622 | 5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */ | 1622 | 5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */ |
1623 | 1, /* uvd_v6_0_enc_ring_insert_end */ | 1623 | 1, /* uvd_v6_0_enc_ring_insert_end */ |
1624 | .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */ | 1624 | .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */ |