diff options
| author | Chunming Zhou <David1.Zhou@amd.com> | 2017-03-23 05:38:34 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-03-29 23:55:30 -0400 |
| commit | 4fb1cf3acee526cb352c42c9f3e66db06b7eef60 (patch) | |
| tree | cc5605f40badd217e0e0544be1c1ede5545b7340 /drivers/gpu/drm/amd/amdgpu | |
| parent | 36f8c1f9037b0a05738ad479320c398f7a4642c1 (diff) | |
drm/amdgpu: set page table depth by num_level
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 |
2 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index 1ff019cda42d..987b21b216f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | |||
| @@ -195,7 +195,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) | |||
| 195 | for (i = 0; i <= 14; i++) { | 195 | for (i = 0; i <= 14; i++) { |
| 196 | tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i); | 196 | tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i); |
| 197 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); | 197 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); |
| 198 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); | 198 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, |
| 199 | adev->vm_manager.num_level); | ||
| 199 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, | 200 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
| 200 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); | 201 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
| 201 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, | 202 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index 7c2075a2c243..128024aba39e 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | |||
| @@ -216,7 +216,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) | |||
| 216 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, | 216 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
| 217 | ENABLE_CONTEXT, 1); | 217 | ENABLE_CONTEXT, 1); |
| 218 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, | 218 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
| 219 | PAGE_TABLE_DEPTH, 1); | 219 | PAGE_TABLE_DEPTH, adev->vm_manager.num_level); |
| 220 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, | 220 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
| 221 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); | 221 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
| 222 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, | 222 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |