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authorMichel Dänzer <michel.daenzer@amd.com>2016-08-03 23:39:38 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-08-10 14:28:07 -0400
commit3fd4b751c5409f4b9bf67d12b26356406b2af94c (patch)
tree9eee617b5fddf08877d09e3de0920dc1fb14cb06 /drivers/gpu/drm/amd/amdgpu
parent325cbba19a32b172300fc87cd4da7c45c4f9e0ba (diff)
drm/amdgpu: Set MASTER_UPDATE_MODE to 0 again
With the previous change, it's safe to let page flips take effect anytime during a vertical blank period. This can avoid delaying a flip by a frame in some cases where we get to amdgpu_flip_work_func -> adev->mode_info.funcs->page_flip during a vertical blank period. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v10_0.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v11_0.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v8_0.c4
3 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index a0964c99e3a9..db6e6c3eaae2 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -646,8 +646,8 @@ static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
646 646
647 if (save->crtc_enabled[i]) { 647 if (save->crtc_enabled[i]) {
648 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]); 648 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
649 if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { 649 if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 0) {
650 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); 650 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 0);
651 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp); 651 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
652 } 652 }
653 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 653 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
@@ -2314,8 +2314,8 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
2314 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2314 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2315 (viewport_w << 16) | viewport_h); 2315 (viewport_w << 16) | viewport_h);
2316 2316
2317 /* set pageflip to happen only at start of vblank interval (front porch) */ 2317 /* set pageflip to happen anywhere in vblank interval */
2318 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); 2318 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2319 2319
2320 if (!atomic && fb && fb != crtc->primary->fb) { 2320 if (!atomic && fb && fb != crtc->primary->fb) {
2321 amdgpu_fb = to_amdgpu_framebuffer(fb); 2321 amdgpu_fb = to_amdgpu_framebuffer(fb);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 7d8417ae0ce6..a35ac3a859ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -2297,8 +2297,8 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
2297 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2297 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2298 (viewport_w << 16) | viewport_h); 2298 (viewport_w << 16) | viewport_h);
2299 2299
2300 /* set pageflip to happen only at start of vblank interval (front porch) */ 2300 /* set pageflip to happen anywhere in vblank interval */
2301 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); 2301 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2302 2302
2303 if (!atomic && fb && fb != crtc->primary->fb) { 2303 if (!atomic && fb && fb != crtc->primary->fb) {
2304 amdgpu_fb = to_amdgpu_framebuffer(fb); 2304 amdgpu_fb = to_amdgpu_framebuffer(fb);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 7badb0022a5e..9fcf74032885 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -2183,8 +2183,8 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
2183 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2183 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2184 (viewport_w << 16) | viewport_h); 2184 (viewport_w << 16) | viewport_h);
2185 2185
2186 /* set pageflip to happen only at start of vblank interval (front porch) */ 2186 /* set pageflip to happen anywhere in vblank interval */
2187 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); 2187 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2188 2188
2189 if (!atomic && fb && fb != crtc->primary->fb) { 2189 if (!atomic && fb && fb != crtc->primary->fb) {
2190 amdgpu_fb = to_amdgpu_framebuffer(fb); 2190 amdgpu_fb = to_amdgpu_framebuffer(fb);