diff options
author | Christian König <christian.koenig@amd.com> | 2018-09-18 04:38:09 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2018-09-19 13:38:10 -0400 |
commit | 3e14bedc581c3b7b05cd36352d0d47eca0317497 (patch) | |
tree | 7bcabe86261f716c24b9523a8a7fbe1e0b0aed0d /drivers/gpu/drm/amd/amdgpu | |
parent | 32f2a0d117769bdca7f7ee6224659f2c688ebc85 (diff) |
drm/amdgpu: remove fence fallback
DC doesn't seem to have a fallback path either.
So when interrupts doesn't work any more we are pretty much busted no
matter what.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 56 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 |
3 files changed, 0 insertions, 58 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index c43bc83c2d29..6cb35e3dab30 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h | |||
@@ -146,7 +146,6 @@ extern int amdgpu_cik_support; | |||
146 | #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ | 146 | #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ |
147 | #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 | 147 | #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 |
148 | #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ | 148 | #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
149 | #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) | ||
150 | /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ | 149 | /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ |
151 | #define AMDGPU_IB_POOL_SIZE 16 | 150 | #define AMDGPU_IB_POOL_SIZE 16 |
152 | #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 | 151 | #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index da36731460b5..176f28777f5e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | |||
@@ -196,19 +196,6 @@ int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s) | |||
196 | } | 196 | } |
197 | 197 | ||
198 | /** | 198 | /** |
199 | * amdgpu_fence_schedule_fallback - schedule fallback check | ||
200 | * | ||
201 | * @ring: pointer to struct amdgpu_ring | ||
202 | * | ||
203 | * Start a timer as fallback to our interrupts. | ||
204 | */ | ||
205 | static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring) | ||
206 | { | ||
207 | mod_timer(&ring->fence_drv.fallback_timer, | ||
208 | jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT); | ||
209 | } | ||
210 | |||
211 | /** | ||
212 | * amdgpu_fence_process - check for fence activity | 199 | * amdgpu_fence_process - check for fence activity |
213 | * | 200 | * |
214 | * @ring: pointer to struct amdgpu_ring | 201 | * @ring: pointer to struct amdgpu_ring |
@@ -229,9 +216,6 @@ void amdgpu_fence_process(struct amdgpu_ring *ring) | |||
229 | 216 | ||
230 | } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq); | 217 | } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq); |
231 | 218 | ||
232 | if (seq != ring->fence_drv.sync_seq) | ||
233 | amdgpu_fence_schedule_fallback(ring); | ||
234 | |||
235 | if (unlikely(seq == last_seq)) | 219 | if (unlikely(seq == last_seq)) |
236 | return; | 220 | return; |
237 | 221 | ||
@@ -263,21 +247,6 @@ void amdgpu_fence_process(struct amdgpu_ring *ring) | |||
263 | } | 247 | } |
264 | 248 | ||
265 | /** | 249 | /** |
266 | * amdgpu_fence_fallback - fallback for hardware interrupts | ||
267 | * | ||
268 | * @work: delayed work item | ||
269 | * | ||
270 | * Checks for fence activity. | ||
271 | */ | ||
272 | static void amdgpu_fence_fallback(struct timer_list *t) | ||
273 | { | ||
274 | struct amdgpu_ring *ring = from_timer(ring, t, | ||
275 | fence_drv.fallback_timer); | ||
276 | |||
277 | amdgpu_fence_process(ring); | ||
278 | } | ||
279 | |||
280 | /** | ||
281 | * amdgpu_fence_wait_empty - wait for all fences to signal | 250 | * amdgpu_fence_wait_empty - wait for all fences to signal |
282 | * | 251 | * |
283 | * @adev: amdgpu device pointer | 252 | * @adev: amdgpu device pointer |
@@ -424,8 +393,6 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, | |||
424 | atomic_set(&ring->fence_drv.last_seq, 0); | 393 | atomic_set(&ring->fence_drv.last_seq, 0); |
425 | ring->fence_drv.initialized = false; | 394 | ring->fence_drv.initialized = false; |
426 | 395 | ||
427 | timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0); | ||
428 | |||
429 | ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1; | 396 | ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1; |
430 | spin_lock_init(&ring->fence_drv.lock); | 397 | spin_lock_init(&ring->fence_drv.lock); |
431 | ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *), | 398 | ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *), |
@@ -501,7 +468,6 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev) | |||
501 | amdgpu_irq_put(adev, ring->fence_drv.irq_src, | 468 | amdgpu_irq_put(adev, ring->fence_drv.irq_src, |
502 | ring->fence_drv.irq_type); | 469 | ring->fence_drv.irq_type); |
503 | drm_sched_fini(&ring->sched); | 470 | drm_sched_fini(&ring->sched); |
504 | del_timer_sync(&ring->fence_drv.fallback_timer); | ||
505 | for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j) | 471 | for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j) |
506 | dma_fence_put(ring->fence_drv.fences[j]); | 472 | dma_fence_put(ring->fence_drv.fences[j]); |
507 | kfree(ring->fence_drv.fences); | 473 | kfree(ring->fence_drv.fences); |
@@ -595,27 +561,6 @@ static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f) | |||
595 | } | 561 | } |
596 | 562 | ||
597 | /** | 563 | /** |
598 | * amdgpu_fence_enable_signaling - enable signalling on fence | ||
599 | * @fence: fence | ||
600 | * | ||
601 | * This function is called with fence_queue lock held, and adds a callback | ||
602 | * to fence_queue that checks if this fence is signaled, and if so it | ||
603 | * signals the fence and removes itself. | ||
604 | */ | ||
605 | static bool amdgpu_fence_enable_signaling(struct dma_fence *f) | ||
606 | { | ||
607 | struct amdgpu_fence *fence = to_amdgpu_fence(f); | ||
608 | struct amdgpu_ring *ring = fence->ring; | ||
609 | |||
610 | if (!timer_pending(&ring->fence_drv.fallback_timer)) | ||
611 | amdgpu_fence_schedule_fallback(ring); | ||
612 | |||
613 | DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); | ||
614 | |||
615 | return true; | ||
616 | } | ||
617 | |||
618 | /** | ||
619 | * amdgpu_fence_free - free up the fence memory | 564 | * amdgpu_fence_free - free up the fence memory |
620 | * | 565 | * |
621 | * @rcu: RCU callback head | 566 | * @rcu: RCU callback head |
@@ -645,7 +590,6 @@ static void amdgpu_fence_release(struct dma_fence *f) | |||
645 | static const struct dma_fence_ops amdgpu_fence_ops = { | 590 | static const struct dma_fence_ops amdgpu_fence_ops = { |
646 | .get_driver_name = amdgpu_fence_get_driver_name, | 591 | .get_driver_name = amdgpu_fence_get_driver_name, |
647 | .get_timeline_name = amdgpu_fence_get_timeline_name, | 592 | .get_timeline_name = amdgpu_fence_get_timeline_name, |
648 | .enable_signaling = amdgpu_fence_enable_signaling, | ||
649 | .release = amdgpu_fence_release, | 593 | .release = amdgpu_fence_release, |
650 | }; | 594 | }; |
651 | 595 | ||
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 9cc239968e40..44fc665e4577 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | |||
@@ -77,7 +77,6 @@ struct amdgpu_fence_driver { | |||
77 | bool initialized; | 77 | bool initialized; |
78 | struct amdgpu_irq_src *irq_src; | 78 | struct amdgpu_irq_src *irq_src; |
79 | unsigned irq_type; | 79 | unsigned irq_type; |
80 | struct timer_list fallback_timer; | ||
81 | unsigned num_fences_mask; | 80 | unsigned num_fences_mask; |
82 | spinlock_t lock; | 81 | spinlock_t lock; |
83 | struct dma_fence **fences; | 82 | struct dma_fence **fences; |