Merge branch 'drm-next-4.16' of git://people.freedesktop.org/~agd5f/linux into drm-next

 A few more fixes for 4.16, nothing major.

A few more fixes for 4.16.  This is on top of the pull request from
last week.  Most notable change here is a fix to the link order for
the now separate from amdgpu GPU scheduler to fix crashes when the
modules are build into the kernel rather than as modules.

* 'drm-next-4.16' of git://people.freedesktop.org/~agd5f/linux:
  drm: fix gpu scheduler link order
  drm/amd/display: Demote error print to debug print when ATOM impl missing
  drm/amdgpu: Avoid leaking PM domain on driver unbind (v2)
  drm/amd/amdgpu: Add Polaris version check
  drm/amdgpu: Reenable manual GPU reset from sysfs
  drm/amdgpu: disable MMHUB power gating on raven
  drm/ttm: Don't unreserve swapped BOs that were previously reserved
  drm/ttm: Don't add swapped BOs to swap-LRU list
  drm/amdgpu: only check for ECC on Vega10
  drm/amd/powerplay: Fix smu_table_entry.handle type
  drm/ttm: add VADDR_FLAG_UPDATED_COUNT to correctly update dma_page global count
  drm/radeon: fill in rb backend map on evergreen/ni.
  drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory (v2)
  drm/ttm: only free pages rather than update global memory count together
  drm/amdgpu: fix CPU based VM updates
  drm/amdgpu: fix typo in amdgpu_vce_validate_bo
  drm/amdgpu: fix amdgpu_vm_pasid_fault_credit
  drm/ttm: check the return value of register_shrinker
  drm/radeon: fix sparse warning: Should it be static?

7 files changed, 51 insertions, 29 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9baf182d5418..00a50cc5ec9a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1874,8 +1874,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
          * ignore it */
         vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
 
-        if (amdgpu_runtime_pm == 1)
-                runtime = true;
         if (amdgpu_device_is_px(ddev))
                 runtime = true;
         if (!pci_is_thunderbolt_attached(adev->pdev))
@@ -2619,7 +2617,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
         uint64_t reset_flags = 0;
         int i, r, resched;
 
-        if (!amdgpu_device_ip_check_soft_reset(adev)) {
+        if (!force && !amdgpu_device_ip_check_soft_reset(adev)) {
                 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
                 return 0;
         }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 55a726a322e3..d274ae535530 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -585,8 +585,8 @@ static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser *p, uint32_t ib_idx,
 
         for (i = 0; i < bo->placement.num_placement; ++i) {
                 bo->placements[i].fpfn = max(bo->placements[i].fpfn, fpfn);
-                bo->placements[i].lpfn = bo->placements[i].fpfn ?
-                        min(bo->placements[i].fpfn, lpfn) : lpfn;
+                bo->placements[i].lpfn = bo->placements[i].lpfn ?
+                        min(bo->placements[i].lpfn, lpfn) : lpfn;
         }
         return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index cd1752b6afa9..6fc16eecf2dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -970,12 +970,16 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
         amdgpu_gart_get_vm_pde(p->adev, AMDGPU_VM_PDB0,
                                &dst, &flags);
 
-        if (parent->base.bo->shadow) {
-                pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow);
-                pde = pd_addr + (entry - parent->entries) * 8;
-                p->func(p, pde, dst, 1, 0, flags);
+        if (p->func == amdgpu_vm_cpu_set_ptes) {
+                pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo);
+        } else {
+                if (parent->base.bo->shadow) {
+                        pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow);
+                        pde = pd_addr + (entry - parent->entries) * 8;
+                        p->func(p, pde, dst, 1, 0, flags);
+                }
+                pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
         }
-        pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
         pde = pd_addr + (entry - parent->entries) * 8;
         p->func(p, pde, dst, 1, 0, flags);
 }
@@ -2478,17 +2482,21 @@ bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev,
 
         spin_lock(&adev->vm_manager.pasid_lock);
         vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
-        spin_unlock(&adev->vm_manager.pasid_lock);
-        if (!vm)
+        if (!vm) {
                 /* VM not found, can't track fault credit */
+                spin_unlock(&adev->vm_manager.pasid_lock);
                 return true;
+        }
 
         /* No lock needed. only accessed by IRQ handler */
-        if (!vm->fault_credit)
+        if (!vm->fault_credit) {
                 /* Too many faults in this VM */
+                spin_unlock(&adev->vm_manager.pasid_lock);
                 return false;
+        }
 
         vm->fault_credit--;
+        spin_unlock(&adev->vm_manager.pasid_lock);
         return true;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index fc270e2ef91a..c06479615e8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1068,8 +1068,8 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
         adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
         adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
         adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
-        adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE);
-        adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
+        adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
+        adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
 
         /* Primitive Buffer */
         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
@@ -1181,13 +1181,14 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
 
         amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
         amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
+                                PACKET3_DMA_DATA_DST_SEL(1) |
                                 PACKET3_DMA_DATA_SRC_SEL(2)));
         amdgpu_ring_write(ring, 0);
         amdgpu_ring_write(ring, 0);
         amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
         amdgpu_ring_write(ring, 0);
-        amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
-
+        amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
+                                adev->gfx.ngg.gds_reserve_size);
 
         gfx_v9_0_write_data_to_reg(ring, 0, false,
                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index eb8b1bb66389..2719937e09d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -634,14 +634,16 @@ static int gmc_v9_0_late_init(void *handle)
         for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
                 BUG_ON(vm_inv_eng[i] > 16);
 
-        r = gmc_v9_0_ecc_available(adev);
-        if (r == 1) {
-                DRM_INFO("ECC is active.\n");
-        } else if (r == 0) {
-                DRM_INFO("ECC is not present.\n");
-        } else {
-                DRM_ERROR("gmc_v9_0_ecc_available() failed. r: %d\n", r);
-                return r;
+        if (adev->asic_type == CHIP_VEGA10) {
+                r = gmc_v9_0_ecc_available(adev);
+                if (r == 1) {
+                        DRM_INFO("ECC is active.\n");
+                } else if (r == 0) {
+                        DRM_INFO("ECC is not present.\n");
+                } else {
+                        DRM_ERROR("gmc_v9_0_ecc_available() failed. r: %d\n", r);
+                        return r;
+                }
         }
 
         return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 8f2cff7b7e0c..a04a033f57de 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -666,8 +666,8 @@ static int soc15_common_early_init(void *handle)
                         AMD_CG_SUPPORT_MC_LS |
                         AMD_CG_SUPPORT_SDMA_MGCG |
                         AMD_CG_SUPPORT_SDMA_LS;
-                adev->pg_flags = AMD_PG_SUPPORT_SDMA |
-                                 AMD_PG_SUPPORT_MMHUB;
+                adev->pg_flags = AMD_PG_SUPPORT_SDMA;
+
                 adev->external_rev_id = 0x1;
                 break;
         default:
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 59271055a30e..b2bfedaf57f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -37,6 +37,9 @@
 #include "gmc/gmc_8_1_d.h"
 #include "vi.h"
 
+/* Polaris10/11/12 firmware version */
+#define FW_1_130_16 ((1 << 24) | (130 << 16) | (16 << 8))
+
 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev);
 
@@ -58,7 +61,9 @@ static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
 */
 static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev)
 {
-        return ((adev->asic_type >= CHIP_POLARIS10) && (adev->asic_type <= CHIP_POLARIS12));
+        return ((adev->asic_type >= CHIP_POLARIS10) &&
+                        (adev->asic_type <= CHIP_POLARIS12) &&
+                        (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16));
 }
 
 /**
@@ -411,7 +416,15 @@ static int uvd_v6_0_sw_init(void *handle)
         if (r)
                 return r;
 
-        if (uvd_v6_0_enc_support(adev)) {
+        if (!uvd_v6_0_enc_support(adev)) {
+                for (i = 0; i < adev->uvd.num_enc_rings; ++i)
+                        adev->uvd.ring_enc[i].funcs = NULL;
+
+                adev->uvd.irq.num_types = 1;
+                adev->uvd.num_enc_rings = 0;
+
+                DRM_INFO("UVD ENC is disabled\n");
+        } else {
                 struct drm_sched_rq *rq;
                 ring = &adev->uvd.ring_enc[0];
                 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];