diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2016-11-01 13:39:10 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-07-14 11:05:48 -0400 |
commit | 219611db30573bab37ff46f4e36571eba0bbd6a5 (patch) | |
tree | 6e0fc24a3daeb86dbbc249cf3988499daff9e8e5 /drivers/gpu/drm/amd/amdgpu | |
parent | cad81e34a8d268146fda82d2379eafb0ce9ea775 (diff) |
drm/amdgpu/gmc7: drop fb location programming
No need to do this as the vbios does this for us. As such
we no longer need to stop the mc during init.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 0fc7d31176a5..31ad68a68c77 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | |||
@@ -266,7 +266,6 @@ static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, | |||
266 | */ | 266 | */ |
267 | static void gmc_v7_0_mc_program(struct amdgpu_device *adev) | 267 | static void gmc_v7_0_mc_program(struct amdgpu_device *adev) |
268 | { | 268 | { |
269 | struct amdgpu_mode_mc_save save; | ||
270 | u32 tmp; | 269 | u32 tmp; |
271 | int i, j; | 270 | int i, j; |
272 | 271 | ||
@@ -280,10 +279,6 @@ static void gmc_v7_0_mc_program(struct amdgpu_device *adev) | |||
280 | } | 279 | } |
281 | WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); | 280 | WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); |
282 | 281 | ||
283 | if (adev->mode_info.num_crtc) | ||
284 | amdgpu_display_set_vga_render_state(adev, false); | ||
285 | |||
286 | gmc_v7_0_mc_stop(adev, &save); | ||
287 | if (gmc_v7_0_wait_for_idle((void *)adev)) { | 282 | if (gmc_v7_0_wait_for_idle((void *)adev)) { |
288 | dev_warn(adev->dev, "Wait for MC idle timedout !\n"); | 283 | dev_warn(adev->dev, "Wait for MC idle timedout !\n"); |
289 | } | 284 | } |
@@ -294,20 +289,12 @@ static void gmc_v7_0_mc_program(struct amdgpu_device *adev) | |||
294 | adev->mc.vram_end >> 12); | 289 | adev->mc.vram_end >> 12); |
295 | WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, | 290 | WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, |
296 | adev->vram_scratch.gpu_addr >> 12); | 291 | adev->vram_scratch.gpu_addr >> 12); |
297 | tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; | ||
298 | tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); | ||
299 | WREG32(mmMC_VM_FB_LOCATION, tmp); | ||
300 | /* XXX double check these! */ | ||
301 | WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8)); | ||
302 | WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); | ||
303 | WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); | ||
304 | WREG32(mmMC_VM_AGP_BASE, 0); | 292 | WREG32(mmMC_VM_AGP_BASE, 0); |
305 | WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); | 293 | WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); |
306 | WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); | 294 | WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); |
307 | if (gmc_v7_0_wait_for_idle((void *)adev)) { | 295 | if (gmc_v7_0_wait_for_idle((void *)adev)) { |
308 | dev_warn(adev->dev, "Wait for MC idle timedout !\n"); | 296 | dev_warn(adev->dev, "Wait for MC idle timedout !\n"); |
309 | } | 297 | } |
310 | gmc_v7_0_mc_resume(adev, &save); | ||
311 | 298 | ||
312 | WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); | 299 | WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); |
313 | 300 | ||