drm/amdgpu: Add sysfs file for PCIe usage v5

Add a sysfs file that reports the number of bytes transmitted and
received in the last second. This can be used to approximate the PCIe
bandwidth usage over the last second.

v2: Clarify use of mps as estimation of bandwidth
v3: Don't make the file on APUs
v4: Early exit for APUs in the read function, change output to
    display "packets-received packets-sent mps"
v5: fix missing header for si (Alex)

Signed-off-by: Kent Russell <kent.russell@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 47 insertions, 0 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 03e7be595a0d..cdc8ab8d79d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -941,6 +941,52 @@ static bool vi_need_full_reset(struct amdgpu_device *adev)
         }
 }
 
+static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
+                              uint64_t *count1)
+{
+        uint32_t perfctr = 0;
+        uint64_t cnt0_of, cnt1_of;
+        int tmp;
+
+        /* This reports 0 on APUs, so return to avoid writing/reading registers
+         * that may or may not be different from their GPU counterparts
+         */
+        if (adev->flags & AMD_IS_APU)
+                return;
+
+        /* Set the 2 events that we wish to watch, defined above */
+        /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
+        perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
+        perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
+
+        /* Write to enable desired perf counters */
+        WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr);
+        /* Zero out and enable the perf counters
+         * Write 0x5:
+         * Bit 0 = Start all counters(1)
+         * Bit 2 = Global counter reset enable(1)
+         */
+        WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005);
+
+        msleep(1000);
+
+        /* Load the shadow and disable the perf counters
+         * Write 0x2:
+         * Bit 0 = Stop counters(0)
+         * Bit 1 = Load the shadow counters(1)
+         */
+        WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002);
+
+        /* Read register values to get any >32bit overflow */
+        tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
+        cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
+        cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
+
+        /* Get the values and add the overflow */
+        *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
+        *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
+}
+
 static const struct amdgpu_asic_funcs vi_asic_funcs =
 {
         .read_disabled_bios = &vi_read_disabled_bios,
@@ -956,6 +1002,7 @@ static const struct amdgpu_asic_funcs vi_asic_funcs =
         .invalidate_hdp = &vi_invalidate_hdp,
         .need_full_reset = &vi_need_full_reset,
         .init_doorbell_index = &legacy_doorbell_index_init,
+        .get_pcie_usage = &vi_get_pcie_usage,
 };
 
 #define CZ_REV_BRISTOL(rev)      \