drm/amdgpu: Add Fiji DID 0x7300 common support

Signed-off-by: David Zhang <david1.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

1 files changed, 34 insertions, 0 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 2095f57c27e1..7d1ae2437309 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -203,6 +203,17 @@ static const u32 tonga_mgcg_cgcg_init[] =
         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 };
 
+static const u32 fiji_mgcg_cgcg_init[] =
+{
+        mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
+        mmPCIE_INDEX, 0xffffffff, 0x0140001c,
+        mmPCIE_DATA, 0x000f0000, 0x00000000,
+        mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
+        mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
+        mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
+        mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
+};
+
 static const u32 iceland_mgcg_cgcg_init[] =
 {
         mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
@@ -232,6 +243,11 @@ static void vi_init_golden_registers(struct amdgpu_device *adev)
                                                  iceland_mgcg_cgcg_init,
                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
                 break;
+        case CHIP_FIJI:
+                amdgpu_program_register_sequence(adev,
+                                                 fiji_mgcg_cgcg_init,
+                                                 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
+                break;
         case CHIP_TONGA:
                 amdgpu_program_register_sequence(adev,
                                                  tonga_mgcg_cgcg_init,
@@ -469,6 +485,7 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
                 asic_register_table = tonga_allowed_read_registers;
                 size = ARRAY_SIZE(tonga_allowed_read_registers);
                 break;
+        case CHIP_FIJI:
         case CHIP_TONGA:
         case CHIP_CARRIZO:
                 asic_register_table = cz_allowed_read_registers;
@@ -1147,6 +1164,18 @@ static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
         },
 };
 
+static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
+{
+        /* ORDER MATTERS! */
+        {
+                .type = AMD_IP_BLOCK_TYPE_COMMON,
+                .major = 2,
+                .minor = 0,
+                .rev = 0,
+                .funcs = &vi_common_ip_funcs,
+        }
+};
+
 static const struct amdgpu_ip_block_version cz_ip_blocks[] =
 {
         /* ORDER MATTERS! */
@@ -1222,6 +1251,10 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
                 adev->ip_blocks = topaz_ip_blocks;
                 adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
                 break;
+        case CHIP_FIJI:
+                adev->ip_blocks = fiji_ip_blocks;
+                adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
+                break;
         case CHIP_TONGA:
                 adev->ip_blocks = tonga_ip_blocks;
                 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
@@ -1299,6 +1332,7 @@ static int vi_common_early_init(void *handle)
                 if (amdgpu_smc_load_fw && smc_enabled)
                         adev->firmware.smu_load = true;
                 break;
+        case CHIP_FIJI:
         case CHIP_TONGA:
                 adev->has_uvd = true;
                 adev->cg_flags = 0;