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authorAlex Deucher <alexander.deucher@amd.com>2018-07-10 17:51:22 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-07-13 15:52:41 -0400
commit3f2ddfa8875ce71a8c12723d1841647af8cbb0ba (patch)
tree79e9a00fa975e1e132e4767c27e8ee1548c62e51 /drivers/gpu/drm/amd/amdgpu/vi.c
parentec95213112dca6111eb7561ae6384f77017dfd1f (diff)
drm/amdgpu/vi: fix mixed up state in smu clockgating setup
Use the PP_STATE_SUPPORT_* rather than AMD_CG_SUPPORT_* when communicating with the SMU. Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vi.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 4ac1288ab7df..42c8ad105b05 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1363,11 +1363,11 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
1363 1363
1364 if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) { 1364 if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
1365 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) { 1365 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
1366 pp_support_state = AMD_CG_SUPPORT_MC_LS; 1366 pp_support_state = PP_STATE_SUPPORT_LS;
1367 pp_state = PP_STATE_LS; 1367 pp_state = PP_STATE_LS;
1368 } 1368 }
1369 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) { 1369 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {
1370 pp_support_state |= AMD_CG_SUPPORT_MC_MGCG; 1370 pp_support_state |= PP_STATE_SUPPORT_CG;
1371 pp_state |= PP_STATE_CG; 1371 pp_state |= PP_STATE_CG;
1372 } 1372 }
1373 if (state == AMD_CG_STATE_UNGATE) 1373 if (state == AMD_CG_STATE_UNGATE)
@@ -1382,11 +1382,11 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
1382 1382
1383 if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) { 1383 if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
1384 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) { 1384 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {
1385 pp_support_state = AMD_CG_SUPPORT_SDMA_LS; 1385 pp_support_state = PP_STATE_SUPPORT_LS;
1386 pp_state = PP_STATE_LS; 1386 pp_state = PP_STATE_LS;
1387 } 1387 }
1388 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) { 1388 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {
1389 pp_support_state |= AMD_CG_SUPPORT_SDMA_MGCG; 1389 pp_support_state |= PP_STATE_SUPPORT_CG;
1390 pp_state |= PP_STATE_CG; 1390 pp_state |= PP_STATE_CG;
1391 } 1391 }
1392 if (state == AMD_CG_STATE_UNGATE) 1392 if (state == AMD_CG_STATE_UNGATE)
@@ -1401,11 +1401,11 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
1401 1401
1402 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) { 1402 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
1403 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 1403 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
1404 pp_support_state = AMD_CG_SUPPORT_HDP_LS; 1404 pp_support_state = PP_STATE_SUPPORT_LS;
1405 pp_state = PP_STATE_LS; 1405 pp_state = PP_STATE_LS;
1406 } 1406 }
1407 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) { 1407 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {
1408 pp_support_state |= AMD_CG_SUPPORT_HDP_MGCG; 1408 pp_support_state |= PP_STATE_SUPPORT_CG;
1409 pp_state |= PP_STATE_CG; 1409 pp_state |= PP_STATE_CG;
1410 } 1410 }
1411 if (state == AMD_CG_STATE_UNGATE) 1411 if (state == AMD_CG_STATE_UNGATE)