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authorJammy Zhou <Jammy.Zhou@amd.com>2015-07-21 23:29:01 -0400
committerAlex Deucher <alexander.deucher@amd.com>2015-08-17 16:50:21 -0400
commit2f7d10b393c83acd3eedc3d6ab94dce29ac6a890 (patch)
treedc13e4604dc31f280f0593123e29450460969fa5 /drivers/gpu/drm/amd/amdgpu/vi.c
parentfa9f1d4e86f67a4df03e153d9b9cd1bd1838767c (diff)
drm/amdgpu: merge amdgpu_family.h into amd_shared.h (v2)
Make the definitions common for all driver components v2: fix kfd Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vi.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 0f4a4f438f5e..2095f57c27e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -261,7 +261,7 @@ static u32 vi_get_xclk(struct amdgpu_device *adev)
261 u32 reference_clock = adev->clock.spll.reference_freq; 261 u32 reference_clock = adev->clock.spll.reference_freq;
262 u32 tmp; 262 u32 tmp;
263 263
264 if (adev->flags & AMDGPU_IS_APU) 264 if (adev->flags & AMD_IS_APU)
265 return reference_clock; 265 return reference_clock;
266 266
267 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); 267 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
@@ -771,7 +771,7 @@ static void vi_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
771 srbm_soft_reset = 771 srbm_soft_reset =
772 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1); 772 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
773 773
774 if (!(adev->flags & AMDGPU_IS_APU)) { 774 if (!(adev->flags & AMD_IS_APU)) {
775 if (reset_mask & AMDGPU_RESET_MC) 775 if (reset_mask & AMDGPU_RESET_MC)
776 srbm_soft_reset = 776 srbm_soft_reset =
777 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 777 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
@@ -991,7 +991,7 @@ static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
991 if (amdgpu_pcie_gen2 == 0) 991 if (amdgpu_pcie_gen2 == 0)
992 return; 992 return;
993 993
994 if (adev->flags & AMDGPU_IS_APU) 994 if (adev->flags & AMD_IS_APU)
995 return; 995 return;
996 996
997 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); 997 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
@@ -1019,7 +1019,7 @@ static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
1019 u32 tmp; 1019 u32 tmp;
1020 1020
1021 /* not necessary on CZ */ 1021 /* not necessary on CZ */
1022 if (adev->flags & AMDGPU_IS_APU) 1022 if (adev->flags & AMD_IS_APU)
1023 return; 1023 return;
1024 1024
1025 tmp = RREG32(mmBIF_DOORBELL_APER_EN); 1025 tmp = RREG32(mmBIF_DOORBELL_APER_EN);
@@ -1268,7 +1268,7 @@ static int vi_common_early_init(void *handle)
1268 bool smc_enabled = false; 1268 bool smc_enabled = false;
1269 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1269 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1270 1270
1271 if (adev->flags & AMDGPU_IS_APU) { 1271 if (adev->flags & AMD_IS_APU) {
1272 adev->smc_rreg = &cz_smc_rreg; 1272 adev->smc_rreg = &cz_smc_rreg;
1273 adev->smc_wreg = &cz_smc_wreg; 1273 adev->smc_wreg = &cz_smc_wreg;
1274 } else { 1274 } else {