diff options
author | Hawking Zhang <Hawking.Zhang@amd.com> | 2017-05-15 06:08:18 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-05-24 18:08:59 -0400 |
commit | fbf09b693579ca92a806e6dde83f6abb4832fc70 (patch) | |
tree | 1503c082b9ae07a20f33d0a7db0025614d5ba082 /drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | |
parent | 04e5f2a63547d8d9eb4a7eda371a9252e779976b (diff) |
drm/amdgpu: correct emit frame size for vcn dec/enc ring
only mmhub will be invalidated during vcn dec/enc vm flush
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 94104a9990aa..ad1862f64aeb 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | |||
@@ -1110,7 +1110,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { | |||
1110 | .set_wptr = vcn_v1_0_dec_ring_set_wptr, | 1110 | .set_wptr = vcn_v1_0_dec_ring_set_wptr, |
1111 | .emit_frame_size = | 1111 | .emit_frame_size = |
1112 | 2 + /* vcn_v1_0_dec_ring_emit_hdp_invalidate */ | 1112 | 2 + /* vcn_v1_0_dec_ring_emit_hdp_invalidate */ |
1113 | 34 * AMDGPU_MAX_VMHUBS + /* vcn_v1_0_dec_ring_emit_vm_flush */ | 1113 | 34 + /* vcn_v1_0_dec_ring_emit_vm_flush */ |
1114 | 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */ | 1114 | 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */ |
1115 | 6, | 1115 | 6, |
1116 | .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */ | 1116 | .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */ |
@@ -1138,7 +1138,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = { | |||
1138 | .get_wptr = vcn_v1_0_enc_ring_get_wptr, | 1138 | .get_wptr = vcn_v1_0_enc_ring_get_wptr, |
1139 | .set_wptr = vcn_v1_0_enc_ring_set_wptr, | 1139 | .set_wptr = vcn_v1_0_enc_ring_set_wptr, |
1140 | .emit_frame_size = | 1140 | .emit_frame_size = |
1141 | 17 * AMDGPU_MAX_VMHUBS + /* vcn_v1_0_enc_ring_emit_vm_flush */ | 1141 | 17 + /* vcn_v1_0_enc_ring_emit_vm_flush */ |
1142 | 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */ | 1142 | 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */ |
1143 | 1, /* vcn_v1_0_enc_ring_insert_end */ | 1143 | 1, /* vcn_v1_0_enc_ring_insert_end */ |
1144 | .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */ | 1144 | .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */ |