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authorHuang Rui <ray.huang@amd.com>2017-04-19 21:42:41 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-05-24 17:41:47 -0400
commitfb4d56fa37240149a29041430a2d0e579e0c9a2e (patch)
tree7cae64f43282bf577969570323a3d57b8a08782f /drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
parent3b8f5ab331079595bc6e397a3d30dd1f2a306ab1 (diff)
drm/amdgpu/vcn: add sw clock gating
Add sw controlled clockgating for VCN. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c207
1 files changed, 205 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 6f26a05b4f5d..15a2c0f10a2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -281,6 +281,207 @@ static void vcn_v1_0_mc_resume(struct amdgpu_device *adev)
281} 281}
282 282
283/** 283/**
284 * vcn_v1_0_disable_clock_gating - disable VCN clock gating
285 *
286 * @adev: amdgpu_device pointer
287 * @sw: enable SW clock gating
288 *
289 * Disable clock gating for VCN block
290 */
291static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev, bool sw)
292{
293 uint32_t data;
294
295 /* JPEG disable CGC */
296 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_CTRL));
297
298 if (sw)
299 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
300 else
301 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK;
302
303 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
304 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
305 WREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_CTRL), data);
306
307 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_GATE));
308 data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
309 WREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_GATE), data);
310
311 /* UVD disable CGC */
312 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL));
313 if (sw)
314 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
315 else
316 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
317
318 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
319 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
320 WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL), data);
321
322 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_GATE));
323 data &= ~(UVD_CGC_GATE__SYS_MASK
324 | UVD_CGC_GATE__UDEC_MASK
325 | UVD_CGC_GATE__MPEG2_MASK
326 | UVD_CGC_GATE__REGS_MASK
327 | UVD_CGC_GATE__RBC_MASK
328 | UVD_CGC_GATE__LMI_MC_MASK
329 | UVD_CGC_GATE__LMI_UMC_MASK
330 | UVD_CGC_GATE__IDCT_MASK
331 | UVD_CGC_GATE__MPRD_MASK
332 | UVD_CGC_GATE__MPC_MASK
333 | UVD_CGC_GATE__LBSI_MASK
334 | UVD_CGC_GATE__LRBBM_MASK
335 | UVD_CGC_GATE__UDEC_RE_MASK
336 | UVD_CGC_GATE__UDEC_CM_MASK
337 | UVD_CGC_GATE__UDEC_IT_MASK
338 | UVD_CGC_GATE__UDEC_DB_MASK
339 | UVD_CGC_GATE__UDEC_MP_MASK
340 | UVD_CGC_GATE__WCB_MASK
341 | UVD_CGC_GATE__VCPU_MASK
342 | UVD_CGC_GATE__SCPU_MASK);
343 WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_GATE), data);
344
345 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL));
346 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
347 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
348 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
349 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
350 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
351 | UVD_CGC_CTRL__SYS_MODE_MASK
352 | UVD_CGC_CTRL__UDEC_MODE_MASK
353 | UVD_CGC_CTRL__MPEG2_MODE_MASK
354 | UVD_CGC_CTRL__REGS_MODE_MASK
355 | UVD_CGC_CTRL__RBC_MODE_MASK
356 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
357 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
358 | UVD_CGC_CTRL__IDCT_MODE_MASK
359 | UVD_CGC_CTRL__MPRD_MODE_MASK
360 | UVD_CGC_CTRL__MPC_MODE_MASK
361 | UVD_CGC_CTRL__LBSI_MODE_MASK
362 | UVD_CGC_CTRL__LRBBM_MODE_MASK
363 | UVD_CGC_CTRL__WCB_MODE_MASK
364 | UVD_CGC_CTRL__VCPU_MODE_MASK
365 | UVD_CGC_CTRL__SCPU_MODE_MASK);
366 WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL), data);
367
368 /* turn on */
369 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_SUVD_CGC_GATE));
370 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
371 | UVD_SUVD_CGC_GATE__SIT_MASK
372 | UVD_SUVD_CGC_GATE__SMP_MASK
373 | UVD_SUVD_CGC_GATE__SCM_MASK
374 | UVD_SUVD_CGC_GATE__SDB_MASK
375 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
376 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
377 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
378 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
379 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
380 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
381 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
382 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
383 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
384 | UVD_SUVD_CGC_GATE__SCLR_MASK
385 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
386 | UVD_SUVD_CGC_GATE__ENT_MASK
387 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
388 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
389 | UVD_SUVD_CGC_GATE__SITE_MASK
390 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
391 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
392 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
393 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
394 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
395 WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_SUVD_CGC_GATE), data);
396
397 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_SUVD_CGC_CTRL));
398 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
399 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
400 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
401 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
402 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
403 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
404 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
405 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
406 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
407 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
408 WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_SUVD_CGC_CTRL), data);
409}
410
411/**
412 * vcn_v1_0_enable_clock_gating - enable VCN clock gating
413 *
414 * @adev: amdgpu_device pointer
415 * @sw: enable SW clock gating
416 *
417 * Enable clock gating for VCN block
418 */
419static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev, bool sw)
420{
421 uint32_t data = 0;
422
423 /* enable JPEG CGC */
424 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_CTRL));
425 if (sw)
426 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
427 else
428 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
429 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
430 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
431 WREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_CTRL), data);
432
433 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_GATE));
434 data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
435 WREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_GATE), data);
436
437 /* enable UVD CGC */
438 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL));
439 if (sw)
440 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
441 else
442 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
443 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
444 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
445 WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL), data);
446
447 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL));
448 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
449 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
450 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
451 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
452 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
453 | UVD_CGC_CTRL__SYS_MODE_MASK
454 | UVD_CGC_CTRL__UDEC_MODE_MASK
455 | UVD_CGC_CTRL__MPEG2_MODE_MASK
456 | UVD_CGC_CTRL__REGS_MODE_MASK
457 | UVD_CGC_CTRL__RBC_MODE_MASK
458 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
459 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
460 | UVD_CGC_CTRL__IDCT_MODE_MASK
461 | UVD_CGC_CTRL__MPRD_MODE_MASK
462 | UVD_CGC_CTRL__MPC_MODE_MASK
463 | UVD_CGC_CTRL__LBSI_MODE_MASK
464 | UVD_CGC_CTRL__LRBBM_MODE_MASK
465 | UVD_CGC_CTRL__WCB_MODE_MASK
466 | UVD_CGC_CTRL__VCPU_MODE_MASK
467 | UVD_CGC_CTRL__SCPU_MODE_MASK);
468 WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL), data);
469
470 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_SUVD_CGC_CTRL));
471 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
472 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
473 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
474 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
475 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
476 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
477 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
478 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
479 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
480 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
481 WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_SUVD_CGC_CTRL), data);
482}
483
484/**
284 * vcn_v1_0_start - start VCN block 485 * vcn_v1_0_start - start VCN block
285 * 486 *
286 * @adev: amdgpu_device pointer 487 * @adev: amdgpu_device pointer
@@ -300,8 +501,7 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
300 vcn_v1_0_mc_resume(adev); 501 vcn_v1_0_mc_resume(adev);
301 502
302 /* disable clock gating */ 503 /* disable clock gating */
303 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL), 0, 504 vcn_v1_0_disable_clock_gating(adev, false);
304 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK);
305 505
306 /* disable interupt */ 506 /* disable interupt */
307 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 507 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
@@ -481,6 +681,9 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev)
481 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 681 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
482 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 682 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
483 683
684 /* enable clock gating */
685 vcn_v1_0_enable_clock_gating(adev, false);
686
484 return 0; 687 return 0;
485} 688}
486 689
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-12 13:48:43 -0400