drm/amdgpu: move waiting for VM flush into gmc_v9_0_emit_flush_gpu_tlb

Keep that at a common place instead of spread over all engines.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 6 insertions, 14 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 294a1bfb59df..d9f597c36b63 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -863,7 +863,6 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
                                             uint64_t pd_addr)
 {
         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
-        unsigned eng = ring->vm_inv_eng;
         uint32_t data0, data1, mask;
 
         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
@@ -873,12 +872,6 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
         data1 = lower_32_bits(pd_addr);
         mask = 0xffffffff;
         vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
-
-        /* wait for flush */
-        data0 = hub->vm_inv_eng0_ack + eng;
-        data1 = 1 << vmid;
-        mask =  1 << vmid;
-        vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
 }
 
 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
@@ -1008,17 +1001,12 @@ static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
                                             uint64_t pd_addr)
 {
         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
-        unsigned eng = ring->vm_inv_eng;
 
         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
 
         /* wait for reg writes */
         vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
                                         lower_32_bits(pd_addr), 0xffffffff);
-
-        /* wait for flush */
-        vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->vm_inv_eng0_ack + eng,
-                                        1 << vmid, 1 << vmid);
 }
 
 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
@@ -1104,7 +1092,9 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
         .set_wptr = vcn_v1_0_dec_ring_set_wptr,
         .emit_frame_size =
                 6 + 6 + /* hdp invalidate / flush */
-                SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 16 + /* vcn_v1_0_dec_ring_emit_vm_flush */
+                SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
+                SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
+                8 + /* vcn_v1_0_dec_ring_emit_vm_flush */
                 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
                 6,
         .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
@@ -1133,7 +1123,9 @@ static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
         .get_wptr = vcn_v1_0_enc_ring_get_wptr,
         .set_wptr = vcn_v1_0_enc_ring_set_wptr,
         .emit_frame_size =
-                SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 8 + /* vcn_v1_0_enc_ring_emit_vm_flush */
+                SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
+                SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
+                4 + /* vcn_v1_0_enc_ring_emit_vm_flush */
                 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
                 1, /* vcn_v1_0_enc_ring_insert_end */
         .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */