diff options
author | Leo Liu <leo.liu@amd.com> | 2017-02-07 11:47:12 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-05-24 17:41:30 -0400 |
commit | 7741cced67aed83d87152a601d58bfb16eda8301 (patch) | |
tree | f6c7461aa65253e9d330b534aa9ad87aa630a309 /drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | |
parent | 8c303c019014afe5842bf4001b4d762f05b3a77e (diff) |
drm/amdgpu: expose vcn RB command
Signed-off-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 9cd6690c6a3f..643e4cecc3f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | |||
@@ -512,7 +512,7 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 | |||
512 | amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); | 512 | amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); |
513 | amdgpu_ring_write(ring, | 513 | amdgpu_ring_write(ring, |
514 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); | 514 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); |
515 | amdgpu_ring_write(ring, 0); | 515 | amdgpu_ring_write(ring, VCN_CMD_FENCE << 1); |
516 | 516 | ||
517 | amdgpu_ring_write(ring, | 517 | amdgpu_ring_write(ring, |
518 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); | 518 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); |
@@ -522,7 +522,7 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 | |||
522 | amdgpu_ring_write(ring, 0); | 522 | amdgpu_ring_write(ring, 0); |
523 | amdgpu_ring_write(ring, | 523 | amdgpu_ring_write(ring, |
524 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); | 524 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); |
525 | amdgpu_ring_write(ring, 2); | 525 | amdgpu_ring_write(ring, VCN_CMD_TRAP << 1); |
526 | } | 526 | } |
527 | 527 | ||
528 | /** | 528 | /** |
@@ -576,7 +576,7 @@ static void vcn_v1_0_dec_vm_reg_write(struct amdgpu_ring *ring, | |||
576 | amdgpu_ring_write(ring, data1); | 576 | amdgpu_ring_write(ring, data1); |
577 | amdgpu_ring_write(ring, | 577 | amdgpu_ring_write(ring, |
578 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); | 578 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); |
579 | amdgpu_ring_write(ring, 8); | 579 | amdgpu_ring_write(ring, VCN_CMD_WRITE_REG << 1); |
580 | } | 580 | } |
581 | 581 | ||
582 | static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring, | 582 | static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring, |
@@ -593,7 +593,7 @@ static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring, | |||
593 | amdgpu_ring_write(ring, mask); | 593 | amdgpu_ring_write(ring, mask); |
594 | amdgpu_ring_write(ring, | 594 | amdgpu_ring_write(ring, |
595 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); | 595 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); |
596 | amdgpu_ring_write(ring, 12); | 596 | amdgpu_ring_write(ring, VCN_CMD_REG_READ_COND_WAIT << 1); |
597 | } | 597 | } |
598 | 598 | ||
599 | static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, | 599 | static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, |