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| author | David S. Miller <davem@davemloft.net> | 2018-03-23 11:24:57 -0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2018-03-23 11:31:58 -0400 |
| commit | 03fe2debbb2771fb90881e4ce8109b09cf772a5c (patch) | |
| tree | fbaf8738296b2e9dcba81c6daef2d515b6c4948c /drivers/gpu/drm/amd/amdgpu/si_dpm.c | |
| parent | 6686c459e1449a3ee5f3fd313b0a559ace7a700e (diff) | |
| parent | f36b7534b83357cf52e747905de6d65b4f7c2512 (diff) | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Fun set of conflict resolutions here...
For the mac80211 stuff, these were fortunately just parallel
adds. Trivially resolved.
In drivers/net/phy/phy.c we had a bug fix in 'net' that moved the
function phy_disable_interrupts() earlier in the file, whilst in
'net-next' the phy_error() call from this function was removed.
In net/ipv4/xfrm4_policy.c, David Ahern's changes to remove the
'rt_table_id' member of rtable collided with a bug fix in 'net' that
added a new struct member "rt_mtu_locked" which needs to be copied
over here.
The mlxsw driver conflict consisted of net-next separating
the span code and definitions into separate files, whilst
a 'net' bug fix made some changes to that moved code.
The mlx5 infiniband conflict resolution was quite non-trivial,
the RDMA tree's merge commit was used as a guide here, and
here are their notes:
====================
Due to bug fixes found by the syzkaller bot and taken into the for-rc
branch after development for the 4.17 merge window had already started
being taken into the for-next branch, there were fairly non-trivial
merge issues that would need to be resolved between the for-rc branch
and the for-next branch. This merge resolves those conflicts and
provides a unified base upon which ongoing development for 4.17 can
be based.
Conflicts:
drivers/infiniband/hw/mlx5/main.c - Commit 42cea83f9524
(IB/mlx5: Fix cleanup order on unload) added to for-rc and
commit b5ca15ad7e61 (IB/mlx5: Add proper representors support)
add as part of the devel cycle both needed to modify the
init/de-init functions used by mlx5. To support the new
representors, the new functions added by the cleanup patch
needed to be made non-static, and the init/de-init list
added by the representors patch needed to be modified to
match the init/de-init list changes made by the cleanup
patch.
Updates:
drivers/infiniband/hw/mlx5/mlx5_ib.h - Update function
prototypes added by representors patch to reflect new function
names as changed by cleanup patch
drivers/infiniband/hw/mlx5/ib_rep.c - Update init/de-init
stage list to match new order from cleanup patch
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/si_dpm.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/si_dpm.c | 50 |
1 files changed, 13 insertions, 37 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c index ce675a7f179a..22f0b7ff3ac9 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | #include "amdgpu_pm.h" | 26 | #include "amdgpu_pm.h" |
| 27 | #include "amdgpu_dpm.h" | 27 | #include "amdgpu_dpm.h" |
| 28 | #include "amdgpu_atombios.h" | 28 | #include "amdgpu_atombios.h" |
| 29 | #include "amd_pcie.h" | ||
| 29 | #include "sid.h" | 30 | #include "sid.h" |
| 30 | #include "r600_dpm.h" | 31 | #include "r600_dpm.h" |
| 31 | #include "si_dpm.h" | 32 | #include "si_dpm.h" |
| @@ -3331,29 +3332,6 @@ static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev, | |||
| 3331 | } | 3332 | } |
| 3332 | } | 3333 | } |
| 3333 | 3334 | ||
| 3334 | static enum amdgpu_pcie_gen r600_get_pcie_gen_support(struct amdgpu_device *adev, | ||
| 3335 | u32 sys_mask, | ||
| 3336 | enum amdgpu_pcie_gen asic_gen, | ||
| 3337 | enum amdgpu_pcie_gen default_gen) | ||
| 3338 | { | ||
| 3339 | switch (asic_gen) { | ||
| 3340 | case AMDGPU_PCIE_GEN1: | ||
| 3341 | return AMDGPU_PCIE_GEN1; | ||
| 3342 | case AMDGPU_PCIE_GEN2: | ||
| 3343 | return AMDGPU_PCIE_GEN2; | ||
| 3344 | case AMDGPU_PCIE_GEN3: | ||
| 3345 | return AMDGPU_PCIE_GEN3; | ||
| 3346 | default: | ||
| 3347 | if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3)) | ||
| 3348 | return AMDGPU_PCIE_GEN3; | ||
| 3349 | else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2)) | ||
| 3350 | return AMDGPU_PCIE_GEN2; | ||
| 3351 | else | ||
| 3352 | return AMDGPU_PCIE_GEN1; | ||
| 3353 | } | ||
| 3354 | return AMDGPU_PCIE_GEN1; | ||
| 3355 | } | ||
| 3356 | |||
| 3357 | static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, | 3335 | static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, |
| 3358 | u32 *p, u32 *u) | 3336 | u32 *p, u32 *u) |
| 3359 | { | 3337 | { |
| @@ -5028,10 +5006,11 @@ static int si_populate_smc_acpi_state(struct amdgpu_device *adev, | |||
| 5028 | table->ACPIState.levels[0].vddc.index, | 5006 | table->ACPIState.levels[0].vddc.index, |
| 5029 | &table->ACPIState.levels[0].std_vddc); | 5007 | &table->ACPIState.levels[0].std_vddc); |
| 5030 | } | 5008 | } |
| 5031 | table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(adev, | 5009 | table->ACPIState.levels[0].gen2PCIE = |
| 5032 | si_pi->sys_pcie_mask, | 5010 | (u8)amdgpu_get_pcie_gen_support(adev, |
| 5033 | si_pi->boot_pcie_gen, | 5011 | si_pi->sys_pcie_mask, |
| 5034 | AMDGPU_PCIE_GEN1); | 5012 | si_pi->boot_pcie_gen, |
| 5013 | AMDGPU_PCIE_GEN1); | ||
| 5035 | 5014 | ||
| 5036 | if (si_pi->vddc_phase_shed_control) | 5015 | if (si_pi->vddc_phase_shed_control) |
| 5037 | si_populate_phase_shedding_value(adev, | 5016 | si_populate_phase_shedding_value(adev, |
| @@ -7168,10 +7147,10 @@ static void si_parse_pplib_clock_info(struct amdgpu_device *adev, | |||
| 7168 | pl->vddc = le16_to_cpu(clock_info->si.usVDDC); | 7147 | pl->vddc = le16_to_cpu(clock_info->si.usVDDC); |
| 7169 | pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); | 7148 | pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); |
| 7170 | pl->flags = le32_to_cpu(clock_info->si.ulFlags); | 7149 | pl->flags = le32_to_cpu(clock_info->si.ulFlags); |
| 7171 | pl->pcie_gen = r600_get_pcie_gen_support(adev, | 7150 | pl->pcie_gen = amdgpu_get_pcie_gen_support(adev, |
| 7172 | si_pi->sys_pcie_mask, | 7151 | si_pi->sys_pcie_mask, |
| 7173 | si_pi->boot_pcie_gen, | 7152 | si_pi->boot_pcie_gen, |
| 7174 | clock_info->si.ucPCIEGen); | 7153 | clock_info->si.ucPCIEGen); |
| 7175 | 7154 | ||
| 7176 | /* patch up vddc if necessary */ | 7155 | /* patch up vddc if necessary */ |
| 7177 | ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc, | 7156 | ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc, |
| @@ -7326,7 +7305,6 @@ static int si_dpm_init(struct amdgpu_device *adev) | |||
| 7326 | struct si_power_info *si_pi; | 7305 | struct si_power_info *si_pi; |
| 7327 | struct atom_clock_dividers dividers; | 7306 | struct atom_clock_dividers dividers; |
| 7328 | int ret; | 7307 | int ret; |
| 7329 | u32 mask; | ||
| 7330 | 7308 | ||
| 7331 | si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); | 7309 | si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); |
| 7332 | if (si_pi == NULL) | 7310 | if (si_pi == NULL) |
| @@ -7336,11 +7314,9 @@ static int si_dpm_init(struct amdgpu_device *adev) | |||
| 7336 | eg_pi = &ni_pi->eg; | 7314 | eg_pi = &ni_pi->eg; |
| 7337 | pi = &eg_pi->rv7xx; | 7315 | pi = &eg_pi->rv7xx; |
| 7338 | 7316 | ||
| 7339 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | 7317 | si_pi->sys_pcie_mask = |
| 7340 | if (ret) | 7318 | (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >> |
| 7341 | si_pi->sys_pcie_mask = 0; | 7319 | CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT; |
| 7342 | else | ||
| 7343 | si_pi->sys_pcie_mask = mask; | ||
| 7344 | si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID; | 7320 | si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID; |
| 7345 | si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev); | 7321 | si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev); |
| 7346 | 7322 | ||
