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authorChristian König <christian.koenig@amd.com>2016-10-05 08:29:38 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-10-25 14:38:36 -0400
commite12f3d7a23c99617f72305a805ed827567a43a9c (patch)
tree826d4091007045c5dc405f4ca0138a965761a34d /drivers/gpu/drm/amd/amdgpu/si_dma.c
parent7bc6be825a2efb00cf8a194e1d0560c92d5a2f6c (diff)
drm/amdgpu: move IB and frame size directly into the engine description
I should have suggested that on the initial patchset. This saves us a few CPU cycles during CS and a bunch of loc. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/si_dma.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si_dma.c25
1 files changed, 7 insertions, 18 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 9f11e3792077..c1c1b5179de5 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -495,22 +495,6 @@ static void si_dma_ring_emit_vm_flush(struct amdgpu_ring *ring,
495 amdgpu_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */ 495 amdgpu_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */
496} 496}
497 497
498static unsigned si_dma_ring_get_emit_ib_size(struct amdgpu_ring *ring)
499{
500 return
501 7 + 3; /* si_dma_ring_emit_ib */
502}
503
504static unsigned si_dma_ring_get_dma_frame_size(struct amdgpu_ring *ring)
505{
506 return
507 3 + /* si_dma_ring_emit_hdp_flush */
508 3 + /* si_dma_ring_emit_hdp_invalidate */
509 6 + /* si_dma_ring_emit_pipeline_sync */
510 12 + /* si_dma_ring_emit_vm_flush */
511 9 + 9 + 9; /* si_dma_ring_emit_fence x3 for user fence, vm fence */
512}
513
514static int si_dma_early_init(void *handle) 498static int si_dma_early_init(void *handle)
515{ 499{
516 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 500 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -783,6 +767,13 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = {
783 .get_rptr = si_dma_ring_get_rptr, 767 .get_rptr = si_dma_ring_get_rptr,
784 .get_wptr = si_dma_ring_get_wptr, 768 .get_wptr = si_dma_ring_get_wptr,
785 .set_wptr = si_dma_ring_set_wptr, 769 .set_wptr = si_dma_ring_set_wptr,
770 .emit_frame_size =
771 3 + /* si_dma_ring_emit_hdp_flush */
772 3 + /* si_dma_ring_emit_hdp_invalidate */
773 6 + /* si_dma_ring_emit_pipeline_sync */
774 12 + /* si_dma_ring_emit_vm_flush */
775 9 + 9 + 9, /* si_dma_ring_emit_fence x3 for user fence, vm fence */
776 .emit_ib_size = 7 + 3, /* si_dma_ring_emit_ib */
786 .emit_ib = si_dma_ring_emit_ib, 777 .emit_ib = si_dma_ring_emit_ib,
787 .emit_fence = si_dma_ring_emit_fence, 778 .emit_fence = si_dma_ring_emit_fence,
788 .emit_pipeline_sync = si_dma_ring_emit_pipeline_sync, 779 .emit_pipeline_sync = si_dma_ring_emit_pipeline_sync,
@@ -793,8 +784,6 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = {
793 .test_ib = si_dma_ring_test_ib, 784 .test_ib = si_dma_ring_test_ib,
794 .insert_nop = amdgpu_ring_insert_nop, 785 .insert_nop = amdgpu_ring_insert_nop,
795 .pad_ib = si_dma_ring_pad_ib, 786 .pad_ib = si_dma_ring_pad_ib,
796 .get_emit_ib_size = si_dma_ring_get_emit_ib_size,
797 .get_dma_frame_size = si_dma_ring_get_dma_frame_size,
798}; 787};
799 788
800static void si_dma_set_ring_funcs(struct amdgpu_device *adev) 789static void si_dma_set_ring_funcs(struct amdgpu_device *adev)