Merge airlied/drm-next into drm-misc-next

Backmerge the main pull request to sync up with all the newly landed
drivers. Otherwise we'll have chaos even before 4.12 started in
earnest.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>

1 files changed, 73 insertions, 17 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index da46992f7b18..b71e3faa40db 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1010,24 +1010,81 @@ static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {
         {PA_SC_RASTER_CONFIG, false, true},
 };
 
-static uint32_t si_read_indexed_register(struct amdgpu_device *adev,
-                                          u32 se_num, u32 sh_num,
-                                          u32 reg_offset)
+static uint32_t si_get_register_value(struct amdgpu_device *adev,
+                                      bool indexed, u32 se_num,
+                                      u32 sh_num, u32 reg_offset)
 {
-        uint32_t val;
+        if (indexed) {
+                uint32_t val;
+                unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
+                unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
+
+                switch (reg_offset) {
+                case mmCC_RB_BACKEND_DISABLE:
+                        return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
+                case mmGC_USER_RB_BACKEND_DISABLE:
+                        return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
+                case mmPA_SC_RASTER_CONFIG:
+                        return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
+                }
 
-        mutex_lock(&adev->grbm_idx_mutex);
-        if (se_num != 0xffffffff || sh_num != 0xffffffff)
-                amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
+                mutex_lock(&adev->grbm_idx_mutex);
+                if (se_num != 0xffffffff || sh_num != 0xffffffff)
+                        amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 
-        val = RREG32(reg_offset);
+                val = RREG32(reg_offset);
 
-        if (se_num != 0xffffffff || sh_num != 0xffffffff)
-                amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
-        mutex_unlock(&adev->grbm_idx_mutex);
-        return val;
+                if (se_num != 0xffffffff || sh_num != 0xffffffff)
+                        amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+                mutex_unlock(&adev->grbm_idx_mutex);
+                return val;
+        } else {
+                unsigned idx;
+
+                switch (reg_offset) {
+                case mmGB_ADDR_CONFIG:
+                        return adev->gfx.config.gb_addr_config;
+                case mmMC_ARB_RAMCFG:
+                        return adev->gfx.config.mc_arb_ramcfg;
+                case mmGB_TILE_MODE0:
+                case mmGB_TILE_MODE1:
+                case mmGB_TILE_MODE2:
+                case mmGB_TILE_MODE3:
+                case mmGB_TILE_MODE4:
+                case mmGB_TILE_MODE5:
+                case mmGB_TILE_MODE6:
+                case mmGB_TILE_MODE7:
+                case mmGB_TILE_MODE8:
+                case mmGB_TILE_MODE9:
+                case mmGB_TILE_MODE10:
+                case mmGB_TILE_MODE11:
+                case mmGB_TILE_MODE12:
+                case mmGB_TILE_MODE13:
+                case mmGB_TILE_MODE14:
+                case mmGB_TILE_MODE15:
+                case mmGB_TILE_MODE16:
+                case mmGB_TILE_MODE17:
+                case mmGB_TILE_MODE18:
+                case mmGB_TILE_MODE19:
+                case mmGB_TILE_MODE20:
+                case mmGB_TILE_MODE21:
+                case mmGB_TILE_MODE22:
+                case mmGB_TILE_MODE23:
+                case mmGB_TILE_MODE24:
+                case mmGB_TILE_MODE25:
+                case mmGB_TILE_MODE26:
+                case mmGB_TILE_MODE27:
+                case mmGB_TILE_MODE28:
+                case mmGB_TILE_MODE29:
+                case mmGB_TILE_MODE30:
+                case mmGB_TILE_MODE31:
+                        idx = (reg_offset - mmGB_TILE_MODE0);
+                        return adev->gfx.config.tile_mode_array[idx];
+                default:
+                        return RREG32(reg_offset);
+                }
+        }
 }
-
 static int si_read_register(struct amdgpu_device *adev, u32 se_num,
                              u32 sh_num, u32 reg_offset, u32 *value)
 {
@@ -1039,10 +1096,9 @@ static int si_read_register(struct amdgpu_device *adev, u32 se_num,
                         continue;
 
                 if (!si_allowed_read_registers[i].untouched)
-                        *value = si_allowed_read_registers[i].grbm_indexed ?
-                                 si_read_indexed_register(adev, se_num,
-                                                           sh_num, reg_offset) :
-                                 RREG32(reg_offset);
+                        *value = si_get_register_value(adev,
+                                                si_allowed_read_registers[i].grbm_indexed,
+                                                se_num, sh_num, reg_offset);
                 return 0;
         }
         return -EINVAL;