Merge tag 'drm-fixes-for-v4.17-rc1' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
 "One omap, and one alsa pm fix (we merged the breaking patch via drm
  tree).

  Otherwise it's two bunches of amdgpu fixes, removing an unneeded file,
  some DC fixes, HDMI audio regression fix, and some vega12 fixes"

* tag 'drm-fixes-for-v4.17-rc1' of git://people.freedesktop.org/~airlied/linux: (27 commits)
  Revert "drm/amd/display: disable CRTCs with NULL FB on their primary plane (V2)"
  Revert "drm/amd/display: fix dereferencing possible ERR_PTR()"
  drm/amd/display: Fix regamma not affecting full-intensity color values
  drm/amd/display: Fix FBC text console corruption
  drm/amd/display: Only register backlight device if embedded panel connected
  drm/amd/display: fix brightness level after resume from suspend
  drm/amd/display: HDMI has no sound after Panel power off/on
  drm/amdgpu: add MP1 and THM hw ip base reg offset
  drm/amdgpu: fix null pointer panic with direct fw loading on gpu reset
  drm/radeon: add PX quirk for Asus K73TK
  drm/omap: fix crash if there's no video PLL
  drm/amdgpu: Fix memory leaks at amdgpu_init() error path
  drm/amdgpu: Fix PCIe lane width calculation
  drm/radeon: Fix PCIe lane width calculation
  drm/amdgpu/si: implement get/set pcie_lanes asic callback
  drm/amdgpu: Add support for SRBM selection v3
  Revert "drm/amdgpu: Don't change preferred domian when fallback GTT v5"
  drm/amd/powerply: fix power reading on Fiji
  drm/amd/powerplay: Enable ACG SS feature
  drm/amdgpu/sdma: fix mask in emit_pipeline_sync
  ...

1 files changed, 67 insertions, 0 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index b154667a8fd9..a675ec6d2811 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1252,6 +1252,71 @@ static void si_invalidate_hdp(struct amdgpu_device *adev,
         }
 }
 
+static int si_get_pcie_lanes(struct amdgpu_device *adev)
+{
+        u32 link_width_cntl;
+
+        if (adev->flags & AMD_IS_APU)
+                return 0;
+
+        link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
+
+        switch ((link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT) {
+        case LC_LINK_WIDTH_X1:
+                return 1;
+        case LC_LINK_WIDTH_X2:
+                return 2;
+        case LC_LINK_WIDTH_X4:
+                return 4;
+        case LC_LINK_WIDTH_X8:
+                return 8;
+        case LC_LINK_WIDTH_X0:
+        case LC_LINK_WIDTH_X16:
+        default:
+                return 16;
+        }
+}
+
+static void si_set_pcie_lanes(struct amdgpu_device *adev, int lanes)
+{
+        u32 link_width_cntl, mask;
+
+        if (adev->flags & AMD_IS_APU)
+                return;
+
+        switch (lanes) {
+        case 0:
+                mask = LC_LINK_WIDTH_X0;
+                break;
+        case 1:
+                mask = LC_LINK_WIDTH_X1;
+                break;
+        case 2:
+                mask = LC_LINK_WIDTH_X2;
+                break;
+        case 4:
+                mask = LC_LINK_WIDTH_X4;
+                break;
+        case 8:
+                mask = LC_LINK_WIDTH_X8;
+                break;
+        case 16:
+                mask = LC_LINK_WIDTH_X16;
+                break;
+        default:
+                DRM_ERROR("invalid pcie lane request: %d\n", lanes);
+                return;
+        }
+
+        link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
+        link_width_cntl &= ~LC_LINK_WIDTH_MASK;
+        link_width_cntl |= mask << LC_LINK_WIDTH_SHIFT;
+        link_width_cntl |= (LC_RECONFIG_NOW |
+                            LC_RECONFIG_ARC_MISSING_ESCAPE);
+
+        WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
+}
+
 static const struct amdgpu_asic_funcs si_asic_funcs =
 {
         .read_disabled_bios = &si_read_disabled_bios,
@@ -1262,6 +1327,8 @@ static const struct amdgpu_asic_funcs si_asic_funcs =
         .get_xclk = &si_get_xclk,
         .set_uvd_clocks = &si_set_uvd_clocks,
         .set_vce_clocks = NULL,
+        .get_pcie_lanes = &si_get_pcie_lanes,
+        .set_pcie_lanes = &si_set_pcie_lanes,
         .get_config_memsize = &si_get_config_memsize,
         .flush_hdp = &si_flush_hdp,
         .invalidate_hdp = &si_invalidate_hdp,