drm/amdgpu: used cached pcie gen info for SI (v2)

Rather than querying it every time we need it.
Also fixes a crash in VM pass through if there is no
root bridge because the cached value fetch already checks
this properly.

v2: fix includes

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=105244
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Rex Zhu<rezhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

1 files changed, 10 insertions, 12 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index f20c4b7414e8..6e61b56bfbfc 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -31,6 +31,7 @@
 #include "amdgpu_uvd.h"
 #include "amdgpu_vce.h"
 #include "atom.h"
+#include "amd_pcie.h"
 #include "amdgpu_powerplay.h"
 #include "sid.h"
 #include "si_ih.h"
@@ -1484,8 +1485,8 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
 {
         struct pci_dev *root = adev->pdev->bus->self;
         int bridge_pos, gpu_pos;
-        u32 speed_cntl, mask, current_data_rate;
-        int ret, i;
+        u32 speed_cntl, current_data_rate;
+        int i;
         u16 tmp16;
 
         if (pci_is_root_bus(adev->pdev->bus))
@@ -1497,23 +1498,20 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
         if (adev->flags & AMD_IS_APU)
                 return;
 
-        ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
-        if (ret != 0)
-                return;
-
-        if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
+        if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
+                                        CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
                 return;
 
         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
         current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
                 LC_CURRENT_DATA_RATE_SHIFT;
-        if (mask & DRM_PCIE_SPEED_80) {
+        if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
                 if (current_data_rate == 2) {
                         DRM_INFO("PCIE gen 3 link speeds already enabled\n");
                         return;
                 }
                 DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
-        } else if (mask & DRM_PCIE_SPEED_50) {
+        } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) {
                 if (current_data_rate == 1) {
                         DRM_INFO("PCIE gen 2 link speeds already enabled\n");
                         return;
@@ -1529,7 +1527,7 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
         if (!gpu_pos)
                 return;
 
-        if (mask & DRM_PCIE_SPEED_80) {
+        if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
                 if (current_data_rate != 2) {
                         u16 bridge_cfg, gpu_cfg;
                         u16 bridge_cfg2, gpu_cfg2;
@@ -1612,9 +1610,9 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
 
         pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
         tmp16 &= ~0xf;
-        if (mask & DRM_PCIE_SPEED_80)
+        if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
                 tmp16 |= 3;
-        else if (mask & DRM_PCIE_SPEED_50)
+        else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
                 tmp16 |= 2;
         else
                 tmp16 |= 1;