Merge branch 'drm-next-4.20' of git://people.freedesktop.org/~agd5f/linux into drm-next

 Add a new list.h helper for doing bulk updates.  Used by ttm.
- Fixes for display underflow on VI APUs at 4K with UVD running
- Endian fixes for powerplay on vega
- DC fixes for interlaced video
- Vega20 powerplay fixes
- RV/RV2/PCO powerplay fixes
- Fix for spurious ACPI events on HG laptops
- Fix a memory leak in DC on driver unload
- Fixes for manual fan control mode switching
- Suspend/resume robustness fixes
- Fix display handling on RV2
- VCN fixes for DPG on PCO
- Misc code cleanups and warning fixes

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181011014739.3117-1-alexander.deucher@amd.com

1 files changed, 7 insertions, 50 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 6d5c8ac64874..6fb3edaba0ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -318,14 +318,13 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
                 if (adev->sdma.instance[i].feature_version >= 20)
                         adev->sdma.instance[i].burst_nop = true;
 
-                if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
-                        info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
-                        info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
-                        info->fw = adev->sdma.instance[i].fw;
-                        header = (const struct common_firmware_header *)info->fw->data;
-                        adev->firmware.fw_size +=
-                                ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
-                }
+                info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
+                info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
+                info->fw = adev->sdma.instance[i].fw;
+                header = (const struct common_firmware_header *)info->fw->data;
+                adev->firmware.fw_size +=
+                        ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+
         }
 out:
         if (err) {
@@ -778,42 +777,6 @@ static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
 }
 
 /**
- * sdma_v3_0_load_microcode - load the sDMA ME ucode
- *
- * @adev: amdgpu_device pointer
- *
- * Loads the sDMA0/1 ucode.
- * Returns 0 for success, -EINVAL if the ucode is not available.
- */
-static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
-{
-        const struct sdma_firmware_header_v1_0 *hdr;
-        const __le32 *fw_data;
-        u32 fw_size;
-        int i, j;
-
-        /* halt the MEs */
-        sdma_v3_0_enable(adev, false);
-
-        for (i = 0; i < adev->sdma.num_instances; i++) {
-                if (!adev->sdma.instance[i].fw)
-                        return -EINVAL;
-                hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
-                amdgpu_ucode_print_sdma_hdr(&hdr->header);
-                fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
-                fw_data = (const __le32 *)
-                        (adev->sdma.instance[i].fw->data +
-                                le32_to_cpu(hdr->header.ucode_array_offset_bytes));
-                WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
-                for (j = 0; j < fw_size; j++)
-                        WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
-                WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
-        }
-
-        return 0;
-}
-
-/**
  * sdma_v3_0_start - setup and start the async dma engines
  *
  * @adev: amdgpu_device pointer
@@ -825,12 +788,6 @@ static int sdma_v3_0_start(struct amdgpu_device *adev)
 {
         int r;
 
-        if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
-                r = sdma_v3_0_load_microcode(adev);
-                if (r)
-                        return r;
-        }
-
         /* disable sdma engine before programing it */
         sdma_v3_0_ctx_switch_enable(adev, false);
         sdma_v3_0_enable(adev, false);