drm/amdgpu: update to use RREG32_SOC15/WREG32_SOC15 for gfxhub

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 64 insertions, 77 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 51efefe77f44..90e6c28568eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -46,32 +46,26 @@ static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
         value &= 0x0000FFFFFFFFF000ULL;
         value |= 0x1; /*valid bit*/
 
-        WREG32(SOC15_REG_OFFSET(GC, 0,
-                                mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
-               lower_32_bits(value));
+        WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+                     lower_32_bits(value));
 
-        WREG32(SOC15_REG_OFFSET(GC, 0,
-                                mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
-               upper_32_bits(value));
+        WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+                     upper_32_bits(value));
 }
 
 static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
 {
         gfxhub_v1_0_init_gart_pt_regs(adev);
 
-        WREG32(SOC15_REG_OFFSET(GC, 0,
-                                mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
-                (u32)(adev->mc.gtt_start >> 12));
-        WREG32(SOC15_REG_OFFSET(GC, 0,
-                                mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
-                (u32)(adev->mc.gtt_start >> 44));
-
-        WREG32(SOC15_REG_OFFSET(GC, 0,
-                                mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
-                (u32)(adev->mc.gtt_end >> 12));
-        WREG32(SOC15_REG_OFFSET(GC, 0,
-                                mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
-                (u32)(adev->mc.gtt_end >> 44));
+        WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
+                     (u32)(adev->mc.gtt_start >> 12));
+        WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
+                     (u32)(adev->mc.gtt_start >> 44));
+
+        WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
+                     (u32)(adev->mc.gtt_end >> 12));
+        WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
+                     (u32)(adev->mc.gtt_end >> 44));
 }
 
 static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
@@ -80,38 +74,34 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
         uint32_t tmp;
 
         /* Disable AGP. */
-        WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BASE), 0);
-        WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_TOP), 0);
-        WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BOT), 0xFFFFFFFF);
+        WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0);
+        WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
+        WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFFFF);
 
         /* Program the system aperture low logical page number. */
-        WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
-                adev->mc.vram_start >> 18);
-        WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),
-                adev->mc.vram_end >> 18);
+        WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
+                     adev->mc.vram_start >> 18);
+        WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+                     adev->mc.vram_end >> 18);
 
         /* Set default page address. */
         value = adev->vram_scratch.gpu_addr - adev->mc.vram_start
                 + adev->vm_manager.vram_base_offset;
-        WREG32(SOC15_REG_OFFSET(GC, 0,
-                                mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),
-               (u32)(value >> 12));
-        WREG32(SOC15_REG_OFFSET(GC, 0,
-                                mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),
-               (u32)(value >> 44));
+        WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
+                     (u32)(value >> 12));
+        WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
+                     (u32)(value >> 44));
 
         /* Program "protection fault". */
-        WREG32(SOC15_REG_OFFSET(GC, 0,
-                                mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
-               (u32)(adev->dummy_page.addr >> 12));
-        WREG32(SOC15_REG_OFFSET(GC, 0,
-                                mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),
-               (u32)((u64)adev->dummy_page.addr >> 44));
-
-        tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2));
+        WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
+                     (u32)(adev->dummy_page.addr >> 12));
+        WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
+                     (u32)((u64)adev->dummy_page.addr >> 44));
+
+        tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2);
         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
-        WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);
+        WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp);
 }
 
 static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
@@ -119,7 +109,7 @@ static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
         uint32_t tmp;
 
         /* Setup TLB control */
-        tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
+        tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
 
         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
@@ -132,7 +122,7 @@ static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
                             MTYPE, MTYPE_UC);/* XXX for emulation. */
         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
 
-        WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
+        WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 }
 
 static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
@@ -140,7 +130,7 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
         uint32_t tmp;
 
         /* Setup L2 cache */
-        tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
+        tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
         /* XXX for emulation, Refer to closed source code.*/
@@ -149,49 +139,46 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
-        WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);
+        WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);
 
-        tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2));
+        tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);
         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
-        WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2), tmp);
+        WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);
 
         tmp = mmVM_L2_CNTL3_DEFAULT;
-        WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), tmp);
+        WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);
 
         tmp = mmVM_L2_CNTL4_DEFAULT;
         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
-        WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);
+        WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp);
 }
 
 static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
 {
         uint32_t tmp;
 
-        tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL));
+        tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);
         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
-        WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp);
+        WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);
 }
 
 static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
 {
-        WREG32(SOC15_REG_OFFSET(GC, 0,
-                                mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32),
-               0XFFFFFFFF);
-        WREG32(SOC15_REG_OFFSET(GC, 0,
-                mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);
-
-        WREG32(SOC15_REG_OFFSET(GC, 0,
-                mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
-        WREG32(SOC15_REG_OFFSET(GC, 0,
-                mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
-
-        WREG32(SOC15_REG_OFFSET(GC, 0,
-                mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
-        WREG32(SOC15_REG_OFFSET(GC, 0,
-                mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
+        WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
+                     0XFFFFFFFF);
+        WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
+                     0x0000000F);
+
+        WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
+                     0);
+        WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
+                     0);
+
+        WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
+        WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
 
 }
 
@@ -254,10 +241,10 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
                  * VF copy registers so vbios post doesn't program them, for
                  * SRIOV driver need to program them
                  */
-                WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE),
-                                adev->mc.vram_start >> 24);
-                WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP),
-                                adev->mc.vram_end >> 24);
+                WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE,
+                             adev->mc.vram_start >> 24);
+                WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP,
+                             adev->mc.vram_end >> 24);
         }
 
         /* GART Enable. */
@@ -284,19 +271,19 @@ void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
                 WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL) + i, 0);
 
         /* Setup TLB control */
-        tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
+        tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
         tmp = REG_SET_FIELD(tmp,
                                 MC_VM_MX_L1_TLB_CNTL,
                                 ENABLE_ADVANCED_DRIVER_MODEL,
                                 0);
-        WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
+        WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 
         /* Setup L2 cache */
-        tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
+        tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
-        WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);
-        WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), 0);
+        WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);
+        WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
 }
 
 /**
@@ -309,7 +296,7 @@ void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
                                           bool value)
 {
         u32 tmp;
-        tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL));
+        tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
                         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
@@ -334,7 +321,7 @@ void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
                         WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
                         EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
-        WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
+        WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
 }
 
 void gfxhub_v1_0_init(struct amdgpu_device *adev)