aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
diff options
context:
space:
mode:
authorNicolai Hähnle <nicolai.haehnle@amd.com>2017-06-13 16:10:45 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-06-29 12:43:52 -0400
commitc94d38f03d4d3edd4a26c6edb80faeceb5c043ad (patch)
treeee1d947632e59b53cc2af9802de3e2a38546d21c /drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
parent44903326516544e819be91bb09152c1649c17212 (diff)
drm/amdgpu/gfx9: support the amdgpu.disable_cu option
This is ported from gfx8. Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 2e6f203fab9e..20345925d254 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4416,6 +4416,20 @@ static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4416 } 4416 }
4417} 4417}
4418 4418
4419static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4420 u32 bitmap)
4421{
4422 u32 data;
4423
4424 if (!bitmap)
4425 return;
4426
4427 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4428 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4429
4430 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
4431}
4432
4419static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) 4433static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4420{ 4434{
4421 u32 data, mask; 4435 u32 data, mask;
@@ -4436,10 +4450,13 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4436{ 4450{
4437 int i, j, k, counter, active_cu_number = 0; 4451 int i, j, k, counter, active_cu_number = 0;
4438 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 4452 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4453 unsigned disable_masks[4 * 2];
4439 4454
4440 if (!adev || !cu_info) 4455 if (!adev || !cu_info)
4441 return -EINVAL; 4456 return -EINVAL;
4442 4457
4458 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
4459
4443 mutex_lock(&adev->grbm_idx_mutex); 4460 mutex_lock(&adev->grbm_idx_mutex);
4444 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4461 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4445 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4462 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
@@ -4447,6 +4464,9 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4447 ao_bitmap = 0; 4464 ao_bitmap = 0;
4448 counter = 0; 4465 counter = 0;
4449 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 4466 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
4467 if (i < 4 && j < 2)
4468 gfx_v9_0_set_user_cu_inactive_bitmap(
4469 adev, disable_masks[i * 2 + j]);
4450 bitmap = gfx_v9_0_get_cu_active_bitmap(adev); 4470 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4451 cu_info->bitmap[i][j] = bitmap; 4471 cu_info->bitmap[i][j] = bitmap;
4452 4472