Merge branch 'drm-next-4.20' of git://people.freedesktop.org/~agd5f/linux into drm-next

More new features and fixes for 4.20:
- Add dynamic powergating support for VCN on picasso
- Scheduler cleanup
- Vega20 support for KFD
- DC cleanups and bug fixes

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180927184348.2696-1-alexander.deucher@amd.com

1 files changed, 67 insertions, 55 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 470dc80f4fe7..2aeef2bb93a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -2049,35 +2049,35 @@ static int gfx_v8_0_sw_init(void *handle)
         adev->gfx.mec.num_queue_per_pipe = 8;
 
         /* KIQ event */
-        r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_INT_IB2, &adev->gfx.kiq.irq);
+        r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_INT_IB2, &adev->gfx.kiq.irq);
         if (r)
                 return r;
 
         /* EOP Event */
-        r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq);
+        r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq);
         if (r)
                 return r;
 
         /* Privileged reg */
-        r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT,
+        r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT,
                               &adev->gfx.priv_reg_irq);
         if (r)
                 return r;
 
         /* Privileged inst */
-        r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT,
+        r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT,
                               &adev->gfx.priv_inst_irq);
         if (r)
                 return r;
 
         /* Add CP EDC/ECC irq  */
-        r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_ECC_ERROR,
+        r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_ECC_ERROR,
                               &adev->gfx.cp_ecc_error_irq);
         if (r)
                 return r;
 
         /* SQ interrupts. */
-        r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG,
+        r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG,
                               &adev->gfx.sq_irq);
         if (r) {
                 DRM_ERROR("amdgpu_irq_add() for SQ failed: %d\n", r);
@@ -3835,7 +3835,7 @@ static void gfx_v8_0_config_init(struct amdgpu_device *adev)
         }
 }
 
-static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
+static void gfx_v8_0_constants_init(struct amdgpu_device *adev)
 {
         u32 tmp, sh_static_mem_cfg;
         int i;
@@ -4208,31 +4208,11 @@ static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
 {
         int r;
-        u32 tmp;
 
         gfx_v8_0_rlc_stop(adev);
-
-        /* disable CG */
-        tmp = RREG32(mmRLC_CGCG_CGLS_CTRL);
-        tmp &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
-                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
-        WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
-        if (adev->asic_type == CHIP_POLARIS11 ||
-            adev->asic_type == CHIP_POLARIS10 ||
-            adev->asic_type == CHIP_POLARIS12 ||
-            adev->asic_type == CHIP_VEGAM) {
-                tmp = RREG32(mmRLC_CGCG_CGLS_CTRL_3D);
-                tmp &= ~0x3;
-                WREG32(mmRLC_CGCG_CGLS_CTRL_3D, tmp);
-        }
-
-        /* disable PG */
-        WREG32(mmRLC_PG_CNTL, 0);
-
         gfx_v8_0_rlc_reset(adev);
         gfx_v8_0_init_pg(adev);
 
-
         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
                 /* legacy rlc firmware loading */
                 r = gfx_v8_0_rlc_load_microcode(adev);
@@ -5039,7 +5019,7 @@ static int gfx_v8_0_hw_init(void *handle)
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
         gfx_v8_0_init_golden_registers(adev);
-        gfx_v8_0_gpu_init(adev);
+        gfx_v8_0_constants_init(adev);
 
         r = gfx_v8_0_rlc_resume(adev);
         if (r)
@@ -5080,6 +5060,55 @@ static int gfx_v8_0_kcq_disable(struct amdgpu_device *adev)
         return r;
 }
 
+static bool gfx_v8_0_is_idle(void *handle)
+{
+        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+        if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)
+                || RREG32(mmGRBM_STATUS2) != 0x8)
+                return false;
+        else
+                return true;
+}
+
+static bool gfx_v8_0_rlc_is_idle(void *handle)
+{
+        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+        if (RREG32(mmGRBM_STATUS2) != 0x8)
+                return false;
+        else
+                return true;
+}
+
+static int gfx_v8_0_wait_for_rlc_idle(void *handle)
+{
+        unsigned int i;
+        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+        for (i = 0; i < adev->usec_timeout; i++) {
+                if (gfx_v8_0_rlc_is_idle(handle))
+                        return 0;
+
+                udelay(1);
+        }
+        return -ETIMEDOUT;
+}
+
+static int gfx_v8_0_wait_for_idle(void *handle)
+{
+        unsigned int i;
+        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+        for (i = 0; i < adev->usec_timeout; i++) {
+                if (gfx_v8_0_is_idle(handle))
+                        return 0;
+
+                udelay(1);
+        }
+        return -ETIMEDOUT;
+}
+
 static int gfx_v8_0_hw_fini(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -5098,9 +5127,16 @@ static int gfx_v8_0_hw_fini(void *handle)
                 pr_debug("For SRIOV client, shouldn't do anything.\n");
                 return 0;
         }
-        gfx_v8_0_cp_enable(adev, false);
-        gfx_v8_0_rlc_stop(adev);
-
+        adev->gfx.rlc.funcs->enter_safe_mode(adev);
+        if (!gfx_v8_0_wait_for_idle(adev))
+                gfx_v8_0_cp_enable(adev, false);
+        else
+                pr_err("cp is busy, skip halt cp\n");
+        if (!gfx_v8_0_wait_for_rlc_idle(adev))
+                gfx_v8_0_rlc_stop(adev);
+        else
+                pr_err("rlc is busy, skip halt rlc\n");
+        adev->gfx.rlc.funcs->exit_safe_mode(adev);
         return 0;
 }
 
@@ -5121,30 +5157,6 @@ static int gfx_v8_0_resume(void *handle)
         return r;
 }
 
-static bool gfx_v8_0_is_idle(void *handle)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-        if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
-                return false;
-        else
-                return true;
-}
-
-static int gfx_v8_0_wait_for_idle(void *handle)
-{
-        unsigned i;
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-        for (i = 0; i < adev->usec_timeout; i++) {
-                if (gfx_v8_0_is_idle(handle))
-                        return 0;
-
-                udelay(1);
-        }
-        return -ETIMEDOUT;
-}
-
 static bool gfx_v8_0_check_soft_reset(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;