drm/amdgpu: take ownership of per-pipe configuration v3

Make amdgpu the owner of all per-pipe state of the HQDs.

This change will allow us to split the queues between kfd and amdgpu
with a queue granularity instead of pipe granularity.

This patch fixes kfd allocating an HDP_EOP region for its 3 pipes which
goes unused.

v2: support for gfx9
v3: fix gfx7 HPD intitialization

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 24 insertions, 9 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 467a0e3ff5a5..8c2241631ade 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1426,18 +1426,33 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
 {
         int r;
         u32 *hpd;
+        size_t mec_hpd_size;
 
-        /*
-         * we assign only 1 pipe because all other pipes will
-         * be handled by KFD
-         */
-        adev->gfx.mec.num_mec = 1;
-        adev->gfx.mec.num_pipe = 1;
-        adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
+        switch (adev->asic_type) {
+        case CHIP_FIJI:
+        case CHIP_TONGA:
+        case CHIP_POLARIS11:
+        case CHIP_POLARIS12:
+        case CHIP_POLARIS10:
+        case CHIP_CARRIZO:
+                adev->gfx.mec.num_mec = 2;
+                break;
+        case CHIP_TOPAZ:
+        case CHIP_STONEY:
+        default:
+                adev->gfx.mec.num_mec = 1;
+                break;
+        }
+
+        adev->gfx.mec.num_pipe_per_mec = 4;
+        adev->gfx.mec.num_queue_per_pipe = 8;
+
+        /* only 1 pipe of the first MEC is owned by amdgpu */
+        mec_hpd_size = 1 * 1 * adev->gfx.mec.num_queue_per_pipe * GFX8_MEC_HPD_SIZE;
 
         if (adev->gfx.mec.hpd_eop_obj == NULL) {
                 r = amdgpu_bo_create(adev,
-                                     adev->gfx.mec.num_queue * GFX8_MEC_HPD_SIZE,
+                                     mec_hpd_size,
                                      PAGE_SIZE, true,
                                      AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
                                      &adev->gfx.mec.hpd_eop_obj);
@@ -1466,7 +1481,7 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
                 return r;
         }
 
-        memset(hpd, 0, adev->gfx.mec.num_queue * GFX8_MEC_HPD_SIZE);
+        memset(hpd, 0, mec_hpd_size);
 
         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);