drm/amdgpu: add a workaround for GDS ordered append hangs with compute queues

I'm not increasing the DRM version because GDS isn't totally without bugs yet.

v2: update emit_ib_size

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 19 insertions, 2 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index a26747681ed6..b8e50a34bdb3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6084,6 +6084,22 @@ static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
 
+        /* Currently, there is a high possibility to get wave ID mismatch
+         * between ME and GDS, leading to a hw deadlock, because ME generates
+         * different wave IDs than the GDS expects. This situation happens
+         * randomly when at least 5 compute pipes use GDS ordered append.
+         * The wave IDs generated by ME are also wrong after suspend/resume.
+         * Those are probably bugs somewhere else in the kernel driver.
+         *
+         * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
+         * GDS to 0 for this ring (me/pipe).
+         */
+        if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
+                amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+                amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START);
+                amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
+        }
+
         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
         amdgpu_ring_write(ring,
 #ifdef __BIG_ENDIAN
@@ -6890,7 +6906,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
                 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
                 VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */
                 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */
-        .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_compute */
+        .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
         .emit_ib = gfx_v8_0_ring_emit_ib_compute,
         .emit_fence = gfx_v8_0_ring_emit_fence_compute,
         .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
@@ -6920,7 +6936,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
                 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
                 17 + /* gfx_v8_0_ring_emit_vm_flush */
                 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_kiq x3 for user fence, vm fence */
-        .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_compute */
+        .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
         .emit_fence = gfx_v8_0_ring_emit_fence_kiq,
         .test_ring = gfx_v8_0_ring_test_ring,
         .insert_nop = amdgpu_ring_insert_nop,
@@ -6996,6 +7012,7 @@ static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
         adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
         adev->gds.gws.total_size = 64;
         adev->gds.oa.total_size = 16;
+        adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);
 
         if (adev->gds.mem.total_size == 64 * 1024) {
                 adev->gds.mem.gfx_partition_size = 4096;