drm/amdgpu: fix mec queue policy on single MEC asics

Fixes hangs on single MEC asics.

Fixes: 2ed286fb434 (drm/amdgpu: new queue policy, take first 2 queues of each pipe v2)
Reviewed-by: Alex Xie <AlexBin.Xie@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 9 insertions, 3 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 4c04e9dec28b..862bc724de42 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2825,9 +2825,15 @@ static void gfx_v7_0_compute_queue_acquire(struct amdgpu_device *adev)
                 if (mec >= adev->gfx.mec.num_mec)
                         break;
 
-                /* policy: amdgpu owns the first two queues of the first MEC */
-                if (mec == 0 && queue < 2)
-                        set_bit(i, adev->gfx.mec.queue_bitmap);
+                if (adev->gfx.mec.num_mec > 1) {
+                        /* policy: amdgpu owns the first two queues of the first MEC */
+                        if (mec == 0 && queue < 2)
+                                set_bit(i, adev->gfx.mec.queue_bitmap);
+                } else {
+                        /* policy: amdgpu owns all queues in the first pipe */
+                        if (mec == 0 && pipe == 0)
+                                set_bit(i, adev->gfx.mec.queue_bitmap);
+                }
         }
 
         /* update the number of active compute rings */