diff options
author | Sean Paul <seanpaul@chromium.org> | 2017-05-18 09:24:30 -0400 |
---|---|---|
committer | Sean Paul <seanpaul@chromium.org> | 2017-05-18 09:24:30 -0400 |
commit | 6b7781b42dc9bc9bcd1523b6c24b876cdda0bef3 (patch) | |
tree | ee55c67e4ea30b9eb44f301ba0bde2e631a26162 /drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | |
parent | 52d9d38c183bf0e09601d875ea31bb53c05dd8cf (diff) | |
parent | e98c58e55f68f8785aebfab1f8c9a03d8de0afe1 (diff) |
Merge remote-tracking branch 'airlied/drm-next' into drm-misc-next
Picking up drm-next @ 4.12-rc1 in order to apply Michal Hocko's vmalloc patch set
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index fa92b04f6b78..f7414cabd4ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | |||
@@ -1935,7 +1935,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) | |||
1935 | INDEX_STRIDE, 3); | 1935 | INDEX_STRIDE, 3); |
1936 | 1936 | ||
1937 | mutex_lock(&adev->srbm_mutex); | 1937 | mutex_lock(&adev->srbm_mutex); |
1938 | for (i = 0; i < adev->vm_manager.num_ids; i++) { | 1938 | for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) { |
1939 | if (i == 0) | 1939 | if (i == 0) |
1940 | sh_mem_base = 0; | 1940 | sh_mem_base = 0; |
1941 | else | 1941 | else |
@@ -2792,7 +2792,7 @@ static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev) | |||
2792 | struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; | 2792 | struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; |
2793 | 2793 | ||
2794 | if (ring->mqd_obj) { | 2794 | if (ring->mqd_obj) { |
2795 | r = amdgpu_bo_reserve(ring->mqd_obj, false); | 2795 | r = amdgpu_bo_reserve(ring->mqd_obj, true); |
2796 | if (unlikely(r != 0)) | 2796 | if (unlikely(r != 0)) |
2797 | dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r); | 2797 | dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r); |
2798 | 2798 | ||
@@ -2810,7 +2810,7 @@ static void gfx_v7_0_mec_fini(struct amdgpu_device *adev) | |||
2810 | int r; | 2810 | int r; |
2811 | 2811 | ||
2812 | if (adev->gfx.mec.hpd_eop_obj) { | 2812 | if (adev->gfx.mec.hpd_eop_obj) { |
2813 | r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); | 2813 | r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, true); |
2814 | if (unlikely(r != 0)) | 2814 | if (unlikely(r != 0)) |
2815 | dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); | 2815 | dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); |
2816 | amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); | 2816 | amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); |
@@ -3359,7 +3359,7 @@ static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev) | |||
3359 | 3359 | ||
3360 | /* save restore block */ | 3360 | /* save restore block */ |
3361 | if (adev->gfx.rlc.save_restore_obj) { | 3361 | if (adev->gfx.rlc.save_restore_obj) { |
3362 | r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false); | 3362 | r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, true); |
3363 | if (unlikely(r != 0)) | 3363 | if (unlikely(r != 0)) |
3364 | dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r); | 3364 | dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r); |
3365 | amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj); | 3365 | amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj); |
@@ -3371,7 +3371,7 @@ static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev) | |||
3371 | 3371 | ||
3372 | /* clear state block */ | 3372 | /* clear state block */ |
3373 | if (adev->gfx.rlc.clear_state_obj) { | 3373 | if (adev->gfx.rlc.clear_state_obj) { |
3374 | r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); | 3374 | r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true); |
3375 | if (unlikely(r != 0)) | 3375 | if (unlikely(r != 0)) |
3376 | dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r); | 3376 | dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r); |
3377 | amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); | 3377 | amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); |
@@ -3383,7 +3383,7 @@ static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev) | |||
3383 | 3383 | ||
3384 | /* clear state block */ | 3384 | /* clear state block */ |
3385 | if (adev->gfx.rlc.cp_table_obj) { | 3385 | if (adev->gfx.rlc.cp_table_obj) { |
3386 | r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false); | 3386 | r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, true); |
3387 | if (unlikely(r != 0)) | 3387 | if (unlikely(r != 0)) |
3388 | dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); | 3388 | dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); |
3389 | amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj); | 3389 | amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj); |