drm/amdgpu: switch ih handling to two levels (v3)

Newer asics have a two levels of irq ids now:
client id - the IP
src id - the interrupt src within the IP

v2: integrated Christian's comments.
v3: fix rebase fail in SI and CIK

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 3 insertions, 3 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 1a1de6499517..7259dedb88b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -3242,15 +3242,15 @@ static int gfx_v6_0_sw_init(void *handle)
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
         int i, r;
 
-        r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
+        r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
         if (r)
                 return r;
 
-        r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
+        r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
         if (r)
                 return r;
 
-        r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
+        r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
         if (r)
                 return r;