diff options
| author | Flora Cui <Flora.Cui@amd.com> | 2016-12-14 01:35:49 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2016-12-20 19:42:12 -0500 |
| commit | 7c0a705e0326a7eed2149eb0b7b30e23897becda (patch) | |
| tree | cfc37ba3e928da492343f11fafb78f4cc458ebd2 /drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | |
| parent | a1f49cc179ce6b7b7758ae3ff5cdb138d0ee0f56 (diff) | |
drm/amdgpu: update golden setting/tiling table of tahiti
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 344 |
1 files changed, 198 insertions, 146 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 558640aee15a..aa4472343901 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | |||
| @@ -656,239 +656,291 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) | |||
| 656 | } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { | 656 | } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { |
| 657 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { | 657 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { |
| 658 | switch (reg_offset) { | 658 | switch (reg_offset) { |
| 659 | case 0: /* non-AA compressed depth or any compressed stencil */ | 659 | case 0: |
| 660 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | 660 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 661 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | 661 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 662 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 662 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | |
| 663 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | | 663 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | |
| 664 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 665 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | 664 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 666 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | 665 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 667 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | 666 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 667 | NUM_BANKS(ADDR_SURF_16_BANK)); | ||
| 668 | break; | 668 | break; |
| 669 | case 1: /* 2xAA/4xAA compressed depth only */ | 669 | case 1: |
| 670 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | 670 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 671 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | 671 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 672 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 672 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | |
| 673 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | | 673 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | |
| 674 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 675 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | 674 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 676 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | 675 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 677 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | 676 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 677 | NUM_BANKS(ADDR_SURF_16_BANK)); | ||
| 678 | break; | 678 | break; |
| 679 | case 2: /* 8xAA compressed depth only */ | 679 | case 2: |
| 680 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | 680 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 681 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | 681 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 682 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 682 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | |
| 683 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | 683 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | |
| 684 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 685 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | 684 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 686 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | 685 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 687 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | 686 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 687 | NUM_BANKS(ADDR_SURF_16_BANK)); | ||
| 688 | break; | 688 | break; |
| 689 | case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */ | 689 | case 3: |
| 690 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | 690 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 691 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | 691 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 692 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 692 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | |
| 693 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | | ||
| 694 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 695 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | 693 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 696 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | 694 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 697 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | 695 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 696 | NUM_BANKS(ADDR_SURF_4_BANK) | | ||
| 697 | TILE_SPLIT(split_equal_to_row_size)); | ||
| 698 | break; | 698 | break; |
| 699 | case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ | 699 | case 4: |
| 700 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | 700 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 701 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | 701 | ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 702 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 702 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)); |
| 703 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | | ||
| 704 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 705 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | ||
| 706 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | ||
| 707 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | ||
| 708 | break; | 703 | break; |
| 709 | case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ | 704 | case 5: |
| 710 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | 705 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 711 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | 706 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 712 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 707 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | |
| 713 | TILE_SPLIT(split_equal_to_row_size) | | 708 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | |
| 714 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 715 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | 709 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 716 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | 710 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 717 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | 711 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 712 | NUM_BANKS(ADDR_SURF_2_BANK)); | ||
| 718 | break; | 713 | break; |
| 719 | case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ | 714 | case 6: |
| 720 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | 715 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 721 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | 716 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 722 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 717 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | |
| 723 | TILE_SPLIT(split_equal_to_row_size) | | 718 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | |
| 724 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 725 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | 719 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 726 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | 720 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | |
| 727 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); | 721 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 722 | NUM_BANKS(ADDR_SURF_2_BANK)); | ||
| 728 | break; | 723 | break; |
| 729 | case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */ | 724 | case 7: |
| 730 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | 725 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 731 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | 726 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 732 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 727 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 733 | TILE_SPLIT(split_equal_to_row_size) | | 728 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | |
| 734 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 735 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | 729 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 736 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | 730 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 737 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | 731 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 732 | NUM_BANKS(ADDR_SURF_2_BANK)); | ||
| 738 | break; | 733 | break; |
| 739 | case 8: /* 1D and 1D Array Surfaces */ | 734 | case 8: |
| 740 | gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | | 735 | gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)); |
| 741 | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | | ||
| 742 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | ||
| 743 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | | ||
| 744 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 745 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | ||
| 746 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | ||
| 747 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | ||
| 748 | break; | 736 | break; |
| 749 | case 9: /* Displayable maps. */ | 737 | case 9: |
| 750 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | 738 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 751 | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | | 739 | ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 752 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 740 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)); |
| 753 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | | ||
| 754 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 755 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | ||
| 756 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | ||
| 757 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | ||
| 758 | break; | 741 | break; |
| 759 | case 10: /* Display 8bpp. */ | 742 | case 10: |
| 760 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | 743 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 761 | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | | 744 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 762 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 745 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | |
| 763 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | 746 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | |
| 764 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 765 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | 747 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 766 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | 748 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 767 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | 749 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 750 | NUM_BANKS(ADDR_SURF_16_BANK)); | ||
| 768 | break; | 751 | break; |
| 769 | case 11: /* Display 16bpp. */ | 752 | case 11: |
| 770 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | 753 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 771 | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | | 754 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 772 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 755 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | |
| 773 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | 756 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | |
| 774 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 775 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | 757 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 776 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | 758 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| 777 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | 759 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 760 | NUM_BANKS(ADDR_SURF_16_BANK)); | ||
| 778 | break; | 761 | break; |
| 779 | case 12: /* Display 32bpp. */ | 762 | case 12: |
| 780 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | 763 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 781 | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | | 764 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 782 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 765 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | |
| 783 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | | 766 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | |
| 784 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 785 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | 767 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 786 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | 768 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 787 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); | 769 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 770 | NUM_BANKS(ADDR_SURF_16_BANK)); | ||
| 788 | break; | 771 | break; |
| 789 | case 13: /* Thin. */ | 772 | case 13: |
| 790 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | 773 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | |
| 791 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | 774 | ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 792 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 775 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)); |
| 793 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | | ||
| 794 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 795 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | ||
| 796 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | ||
| 797 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | ||
| 798 | break; | 776 | break; |
| 799 | case 14: /* Thin 8 bpp. */ | 777 | case 14: |
| 800 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | 778 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | |
| 801 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | 779 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 802 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 780 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | |
| 803 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | 781 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | |
| 804 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 805 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | 782 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 806 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | 783 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 807 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); | 784 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 785 | NUM_BANKS(ADDR_SURF_16_BANK)); | ||
| 808 | break; | 786 | break; |
| 809 | case 15: /* Thin 16 bpp. */ | 787 | case 15: |
| 810 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | 788 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | |
| 811 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | 789 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 812 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 790 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | |
| 813 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | 791 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | |
| 814 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 815 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | 792 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 816 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | 793 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| 817 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); | 794 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 795 | NUM_BANKS(ADDR_SURF_16_BANK)); | ||
| 818 | break; | 796 | break; |
| 819 | case 16: /* Thin 32 bpp. */ | 797 | case 16: |
| 820 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | 798 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | |
| 821 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | 799 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 822 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 800 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | |
| 823 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | | 801 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | |
| 824 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 825 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | 802 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 826 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | 803 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 827 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); | 804 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 805 | NUM_BANKS(ADDR_SURF_16_BANK)); | ||
| 828 | break; | 806 | break; |
| 829 | case 17: /* Thin 64 bpp. */ | 807 | case 17: |
| 830 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | 808 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | |
| 831 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | 809 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 832 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 810 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | |
| 833 | TILE_SPLIT(split_equal_to_row_size) | | 811 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 812 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | ||
| 813 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | | ||
| 834 | NUM_BANKS(ADDR_SURF_16_BANK) | | 814 | NUM_BANKS(ADDR_SURF_16_BANK) | |
| 815 | TILE_SPLIT(split_equal_to_row_size)); | ||
| 816 | break; | ||
| 817 | case 18: | ||
| 818 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | ||
| 819 | ARRAY_MODE(ARRAY_1D_TILED_THICK) | | ||
| 820 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)); | ||
| 821 | break; | ||
| 822 | case 19: | ||
| 823 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | ||
| 824 | ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | | ||
| 825 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | ||
| 835 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | 826 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 836 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | 827 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 837 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); | 828 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 829 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 830 | TILE_SPLIT(split_equal_to_row_size)); | ||
| 838 | break; | 831 | break; |
| 839 | case 21: /* 8 bpp PRT. */ | 832 | case 20: |
| 840 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | 833 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | |
| 841 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | 834 | ARRAY_MODE(ARRAY_2D_TILED_THICK) | |
| 842 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 835 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | |
| 843 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | 836 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 837 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | ||
| 838 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | | ||
| 844 | NUM_BANKS(ADDR_SURF_16_BANK) | | 839 | NUM_BANKS(ADDR_SURF_16_BANK) | |
| 845 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | | 840 | TILE_SPLIT(split_equal_to_row_size)); |
| 846 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | ||
| 847 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | ||
| 848 | break; | 841 | break; |
| 849 | case 22: /* 16 bpp PRT */ | 842 | case 21: |
| 850 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | 843 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | |
| 851 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | 844 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 845 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | ||
| 846 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | ||
| 847 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | ||
| 848 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | | ||
| 849 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | | ||
| 850 | NUM_BANKS(ADDR_SURF_4_BANK)); | ||
| 851 | break; | ||
| 852 | case 22: | ||
| 853 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | ||
| 854 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | ||
| 852 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 855 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | |
| 853 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | 856 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | |
| 854 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 855 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | 857 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 856 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | 858 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 857 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); | 859 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 860 | NUM_BANKS(ADDR_SURF_4_BANK)); | ||
| 858 | break; | 861 | break; |
| 859 | case 23: /* 32 bpp PRT */ | 862 | case 23: |
| 860 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | 863 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | |
| 861 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | 864 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 862 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 865 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | |
| 863 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | 866 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | |
| 864 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 865 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | 867 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 866 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | 868 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | |
| 867 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | 869 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 870 | NUM_BANKS(ADDR_SURF_2_BANK)); | ||
| 868 | break; | 871 | break; |
| 869 | case 24: /* 64 bpp PRT */ | 872 | case 24: |
| 870 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | 873 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | |
| 871 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | 874 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 872 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 875 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | |
| 873 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | | 876 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | |
| 874 | NUM_BANKS(ADDR_SURF_16_BANK) | | ||
| 875 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | 877 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 876 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | 878 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 877 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | 879 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 880 | NUM_BANKS(ADDR_SURF_2_BANK)); | ||
| 878 | break; | 881 | break; |
| 879 | case 25: /* 128 bpp PRT */ | 882 | case 25: |
| 880 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | 883 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | |
| 881 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | 884 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 882 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | 885 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 883 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | | 886 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | |
| 884 | NUM_BANKS(ADDR_SURF_8_BANK) | | ||
| 885 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | 887 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 886 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | 888 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 887 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); | 889 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 890 | NUM_BANKS(ADDR_SURF_2_BANK)); | ||
| 888 | break; | 891 | break; |
| 889 | default: | 892 | case 26: |
| 890 | gb_tile_moden = 0; | 893 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | |
| 894 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | ||
| 895 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | ||
| 896 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | | ||
| 897 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | ||
| 898 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | ||
| 899 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | | ||
| 900 | NUM_BANKS(ADDR_SURF_2_BANK)); | ||
| 901 | break; | ||
| 902 | case 27: | ||
| 903 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | ||
| 904 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | ||
| 905 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | ||
| 906 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | | ||
| 907 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | ||
| 908 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | ||
| 909 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | | ||
| 910 | NUM_BANKS(ADDR_SURF_2_BANK)); | ||
| 891 | break; | 911 | break; |
| 912 | case 28: | ||
| 913 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | ||
| 914 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | ||
| 915 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | ||
| 916 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | | ||
| 917 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | ||
| 918 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | ||
| 919 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | | ||
| 920 | NUM_BANKS(ADDR_SURF_2_BANK)); | ||
| 921 | break; | ||
| 922 | case 29: | ||
| 923 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | ||
| 924 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | ||
| 925 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | ||
| 926 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | | ||
| 927 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | ||
| 928 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | ||
| 929 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | | ||
| 930 | NUM_BANKS(ADDR_SURF_2_BANK)); | ||
| 931 | break; | ||
| 932 | case 30: | ||
| 933 | gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | ||
| 934 | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | ||
| 935 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | ||
| 936 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | | ||
| 937 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | ||
| 938 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | ||
| 939 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | | ||
| 940 | NUM_BANKS(ADDR_SURF_2_BANK)); | ||
| 941 | break; | ||
| 942 | default: | ||
| 943 | continue; | ||
| 892 | } | 944 | } |
| 893 | adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; | 945 | adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; |
| 894 | WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); | 946 | WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); |