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authorTom St Denis <tom.stdenis@amd.com>2016-12-05 13:24:07 -0500
committerAlex Deucher <alexander.deucher@amd.com>2016-12-08 14:12:17 -0500
commit34e646f44412b366940d859686449f1d02496905 (patch)
tree3da8d66e90af7558070f2d16ba9819d430faae3c /drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
parentc5a60ce81b4962d35a6bbb328fb234d33254cfb7 (diff)
drm/amd/amdgpu: Add gpr reading for GFX v6
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c25
1 files changed, 25 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 879a94bbfe12..558640aee15a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2827,6 +2827,21 @@ static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_
2827 return RREG32(mmSQ_IND_DATA); 2827 return RREG32(mmSQ_IND_DATA);
2828} 2828}
2829 2829
2830static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
2831 uint32_t wave, uint32_t thread,
2832 uint32_t regno, uint32_t num, uint32_t *out)
2833{
2834 WREG32(mmSQ_IND_INDEX,
2835 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2836 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2837 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
2838 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
2839 (SQ_IND_INDEX__FORCE_READ_MASK) |
2840 (SQ_IND_INDEX__AUTO_INCR_MASK));
2841 while (num--)
2842 *(out++) = RREG32(mmSQ_IND_DATA);
2843}
2844
2830static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 2845static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
2831{ 2846{
2832 /* type 0 wave data */ 2847 /* type 0 wave data */
@@ -2851,10 +2866,20 @@ static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, u
2851 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 2866 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
2852} 2867}
2853 2868
2869static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
2870 uint32_t wave, uint32_t start,
2871 uint32_t size, uint32_t *dst)
2872{
2873 wave_read_regs(
2874 adev, simd, wave, 0,
2875 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
2876}
2877
2854static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { 2878static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
2855 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter, 2879 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
2856 .select_se_sh = &gfx_v6_0_select_se_sh, 2880 .select_se_sh = &gfx_v6_0_select_se_sh,
2857 .read_wave_data = &gfx_v6_0_read_wave_data, 2881 .read_wave_data = &gfx_v6_0_read_wave_data,
2882 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
2858}; 2883};
2859 2884
2860static int gfx_v6_0_early_init(void *handle) 2885static int gfx_v6_0_early_init(void *handle)