diff options
author | Mario Kleiner <mario.kleiner.de@gmail.com> | 2015-07-03 00:03:07 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2015-07-08 12:41:37 -0400 |
commit | bd833144a23dead304744dc748f5d72d7e92d315 (patch) | |
tree | 976ed3f7269940d71f7e157cfce70457d28c1a83 /drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | |
parent | 07f18f0bb8d8d65badd8b4988b40d329fc0cc6dc (diff) |
drm/amdgpu: Handle irqs only based on irq ring, not irq status regs.
This is a translation of the patch ...
"drm/radeon: Handle irqs only based on irq ring, not irq status regs."
... for the vblank irq handling, to fix the same problem described
in that patch on the new driver.
Only compile tested due to lack of suitable hw.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
CC: Michel Dänzer <michel.daenzer@amd.com>
CC: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/dce_v11_0.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 95efd98b202d..7f7abb0e0be5 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | |||
@@ -3402,19 +3402,25 @@ static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, | |||
3402 | 3402 | ||
3403 | switch (entry->src_data) { | 3403 | switch (entry->src_data) { |
3404 | case 0: /* vblank */ | 3404 | case 0: /* vblank */ |
3405 | if (disp_int & interrupt_status_offsets[crtc].vblank) { | 3405 | if (disp_int & interrupt_status_offsets[crtc].vblank) |
3406 | dce_v11_0_crtc_vblank_int_ack(adev, crtc); | 3406 | dce_v11_0_crtc_vblank_int_ack(adev, crtc); |
3407 | if (amdgpu_irq_enabled(adev, source, irq_type)) { | 3407 | else |
3408 | drm_handle_vblank(adev->ddev, crtc); | 3408 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
3409 | } | 3409 | |
3410 | DRM_DEBUG("IH: D%d vblank\n", crtc + 1); | 3410 | if (amdgpu_irq_enabled(adev, source, irq_type)) { |
3411 | drm_handle_vblank(adev->ddev, crtc); | ||
3411 | } | 3412 | } |
3413 | DRM_DEBUG("IH: D%d vblank\n", crtc + 1); | ||
3414 | |||
3412 | break; | 3415 | break; |
3413 | case 1: /* vline */ | 3416 | case 1: /* vline */ |
3414 | if (disp_int & interrupt_status_offsets[crtc].vline) { | 3417 | if (disp_int & interrupt_status_offsets[crtc].vline) |
3415 | dce_v11_0_crtc_vline_int_ack(adev, crtc); | 3418 | dce_v11_0_crtc_vline_int_ack(adev, crtc); |
3416 | DRM_DEBUG("IH: D%d vline\n", crtc + 1); | 3419 | else |
3417 | } | 3420 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
3421 | |||
3422 | DRM_DEBUG("IH: D%d vline\n", crtc + 1); | ||
3423 | |||
3418 | break; | 3424 | break; |
3419 | default: | 3425 | default: |
3420 | DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); | 3426 | DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); |