drm/amdgpu: Make SDMA phase quantum configurable

Set a configurable SDMA phase quantum when enabling SDMA context
switching. The default value significantly reduces SDMA latency
in page table updates when user-mode SDMA queues have concurrent
activity, compared to the initial HW setting.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Andres Rodriguez <andres.rodriguez@amd.com>
Reviewed-by: Shaoyun Liu <shaoyun.liu@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 31 insertions, 1 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 4a9cea03f54f..f508f4d01e4a 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -351,14 +351,44 @@ static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
  */
 static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 {
-        u32 f32_cntl;
+        u32 f32_cntl, phase_quantum = 0;
         int i;
 
+        if (amdgpu_sdma_phase_quantum) {
+                unsigned value = amdgpu_sdma_phase_quantum;
+                unsigned unit = 0;
+
+                while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
+                                SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
+                        value = (value + 1) >> 1;
+                        unit++;
+                }
+                if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
+                            SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
+                        value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
+                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
+                        unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
+                                SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
+                        WARN_ONCE(1,
+                        "clamping sdma_phase_quantum to %uK clock cycles\n",
+                                  value << unit);
+                }
+                phase_quantum =
+                        value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
+                        unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
+        }
+
         for (i = 0; i < adev->sdma.num_instances; i++) {
                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
                 if (enable) {
                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
                                         AUTO_CTXSW_ENABLE, 1);
+                        if (amdgpu_sdma_phase_quantum) {
+                                WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
+                                       phase_quantum);
+                                WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
+                                       phase_quantum);
+                        }
                 } else {
                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
                                         AUTO_CTXSW_ENABLE, 0);