Merge tag 'gpmc-omap-fixes-for-v4.7' of https://github.com/rogerq/linux into fixes

OMAP-GPMC: Fixes for for v4.7-rc cycle:

- Fix omap gpmc EXTRADELAY timing. The DT provided timings
were wrongly used causing devices requiring extra delay timing
to fail.

* tag 'gpmc-omap-fixes-for-v4.7' of https://github.com/rogerq/linux:
  memory: omap-gpmc: Fix omap gpmc EXTRADELAY timing
  + Linux 4.7-rc3

Signed-off-by: Olof Johansson <olof@lixom.net>

1 files changed, 20 insertions, 2 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 518dca43b133..9dc4e24e31e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -66,6 +66,16 @@ MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
 
 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
 
+
+static void cik_sdma_free_microcode(struct amdgpu_device *adev)
+{
+        int i;
+        for (i = 0; i < adev->sdma.num_instances; i++) {
+                        release_firmware(adev->sdma.instance[i].fw);
+                        adev->sdma.instance[i].fw = NULL;
+        }
+}
+
 /*
  * sDMA - System DMA
  * Starting with CIK, the GPU has new asynchronous
@@ -419,6 +429,8 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
                 /* Initialize the ring buffer's read and write pointers */
                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
+                WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
+                WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 
                 /* set the wb address whether it's enabled or not */
                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
@@ -446,7 +458,12 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 
                 ring->ready = true;
+        }
+
+        cik_sdma_enable(adev, true);
 
+        for (i = 0; i < adev->sdma.num_instances; i++) {
+                ring = &adev->sdma.instance[i].ring;
                 r = amdgpu_ring_test_ring(ring);
                 if (r) {
                         ring->ready = false;
@@ -529,8 +546,8 @@ static int cik_sdma_start(struct amdgpu_device *adev)
         if (r)
                 return r;
 
-        /* unhalt the MEs */
-        cik_sdma_enable(adev, true);
+        /* halt the engine before programing */
+        cik_sdma_enable(adev, false);
 
         /* start the gfx rings and rlc compute queues */
         r = cik_sdma_gfx_resume(adev);
@@ -998,6 +1015,7 @@ static int cik_sdma_sw_fini(void *handle)
         for (i = 0; i < adev->sdma.num_instances; i++)
                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 
+        cik_sdma_free_microcode(adev);
         return 0;
 }