diff options
author | Christian König <christian.koenig@amd.com> | 2018-01-19 09:19:16 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2018-02-19 14:18:22 -0500 |
commit | 2ee150cda7bdc766cf9baca3534f3a2c0b0e8357 (patch) | |
tree | d9b67b8e56fba3aae616aa72381438dc65420f52 /drivers/gpu/drm/amd/amdgpu/cik_sdma.c | |
parent | 1b9d17db1cb103f56a69d8610d7339fb0a2a90cc (diff) |
drm/amdgpu: remove now superflous *_hdp operation
All HDP invalidation and most flush can now be replaced by the generic
ASIC function.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/cik_sdma.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 1d32dedb2534..5d18512cd090 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c | |||
@@ -261,13 +261,6 @@ static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring) | |||
261 | amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ | 261 | amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ |
262 | } | 262 | } |
263 | 263 | ||
264 | static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) | ||
265 | { | ||
266 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | ||
267 | amdgpu_ring_write(ring, mmHDP_DEBUG0); | ||
268 | amdgpu_ring_write(ring, 1); | ||
269 | } | ||
270 | |||
271 | /** | 264 | /** |
272 | * cik_sdma_ring_emit_fence - emit a fence on the DMA ring | 265 | * cik_sdma_ring_emit_fence - emit a fence on the DMA ring |
273 | * | 266 | * |
@@ -1277,7 +1270,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { | |||
1277 | .set_wptr = cik_sdma_ring_set_wptr, | 1270 | .set_wptr = cik_sdma_ring_set_wptr, |
1278 | .emit_frame_size = | 1271 | .emit_frame_size = |
1279 | 6 + /* cik_sdma_ring_emit_hdp_flush */ | 1272 | 6 + /* cik_sdma_ring_emit_hdp_flush */ |
1280 | 3 + /* cik_sdma_ring_emit_hdp_invalidate */ | 1273 | 3 + /* hdp invalidate */ |
1281 | 6 + /* cik_sdma_ring_emit_pipeline_sync */ | 1274 | 6 + /* cik_sdma_ring_emit_pipeline_sync */ |
1282 | CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */ | 1275 | CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */ |
1283 | 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */ | 1276 | 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */ |
@@ -1287,7 +1280,6 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { | |||
1287 | .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync, | 1280 | .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync, |
1288 | .emit_vm_flush = cik_sdma_ring_emit_vm_flush, | 1281 | .emit_vm_flush = cik_sdma_ring_emit_vm_flush, |
1289 | .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, | 1282 | .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, |
1290 | .emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate, | ||
1291 | .test_ring = cik_sdma_ring_test_ring, | 1283 | .test_ring = cik_sdma_ring_test_ring, |
1292 | .test_ib = cik_sdma_ring_test_ib, | 1284 | .test_ib = cik_sdma_ring_test_ib, |
1293 | .insert_nop = cik_sdma_ring_insert_nop, | 1285 | .insert_nop = cik_sdma_ring_insert_nop, |