diff options
author | Christian König <christian.koenig@amd.com> | 2018-09-18 08:24:49 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2019-01-14 15:04:47 -0500 |
commit | d81f78b440f314e2a551d938e4c509fca16a8fe7 (patch) | |
tree | f8ffd8455c23b8410ea33ca47e8321be79e96b9b /drivers/gpu/drm/amd/amdgpu/cik_ih.c | |
parent | 8bb9eb480d032418bd08d0a6a39e4eaa1dec2fb8 (diff) |
drm/amdgpu: simplify IH programming
Calculate all the addresses and pointers in amdgpu_ih.c
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/cik_ih.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/cik_ih.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c index 884aa9b81e86..721c757156e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c | |||
@@ -103,9 +103,9 @@ static void cik_ih_disable_interrupts(struct amdgpu_device *adev) | |||
103 | */ | 103 | */ |
104 | static int cik_ih_irq_init(struct amdgpu_device *adev) | 104 | static int cik_ih_irq_init(struct amdgpu_device *adev) |
105 | { | 105 | { |
106 | struct amdgpu_ih_ring *ih = &adev->irq.ih; | ||
106 | int rb_bufsz; | 107 | int rb_bufsz; |
107 | u32 interrupt_cntl, ih_cntl, ih_rb_cntl; | 108 | u32 interrupt_cntl, ih_cntl, ih_rb_cntl; |
108 | u64 wptr_off; | ||
109 | 109 | ||
110 | /* disable irqs */ | 110 | /* disable irqs */ |
111 | cik_ih_disable_interrupts(adev); | 111 | cik_ih_disable_interrupts(adev); |
@@ -131,9 +131,8 @@ static int cik_ih_irq_init(struct amdgpu_device *adev) | |||
131 | ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK; | 131 | ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK; |
132 | 132 | ||
133 | /* set the writeback address whether it's enabled or not */ | 133 | /* set the writeback address whether it's enabled or not */ |
134 | wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); | 134 | WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); |
135 | WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); | 135 | WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); |
136 | WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); | ||
137 | 136 | ||
138 | WREG32(mmIH_RB_CNTL, ih_rb_cntl); | 137 | WREG32(mmIH_RB_CNTL, ih_rb_cntl); |
139 | 138 | ||
@@ -188,7 +187,7 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev, | |||
188 | { | 187 | { |
189 | u32 wptr, tmp; | 188 | u32 wptr, tmp; |
190 | 189 | ||
191 | wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]); | 190 | wptr = le32_to_cpu(*ih->wptr_cpu); |
192 | 191 | ||
193 | if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { | 192 | if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { |
194 | wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; | 193 | wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; |