Merge branch 'drm-next-4.13' of git://people.freedesktop.org/~agd5f/linux into drm-next

New radeon and amdgpu features for 4.13:
- Lots of Vega10 bug fixes
- Preliminary Raven support
- KIQ support for compute rings
- MEC queue management rework from Andres
- Audio support for DCE6
- SR-IOV improvements
- Improved module parameters for controlling radeon vs amdgpu support
  for SI and CIK
- Bug fixes
- General code cleanups

[airlied: dropped drmP.h header from one file was needed and build broke]

* 'drm-next-4.13' of git://people.freedesktop.org/~agd5f/linux: (362 commits)
  drm/amdgpu: Fix compiler warnings
  drm/amdgpu: vm_update_ptes remove code duplication
  drm/amd/amdgpu: Port VCN over to new SOC15 macros
  drm/amd/amdgpu: Port PSP v10.0 over to new SOC15 macros
  drm/amd/amdgpu: Port PSP v3.1 over to new SOC15 macros
  drm/amd/amdgpu: Port NBIO v7.0 driver over to new SOC15 macros
  drm/amd/amdgpu: Port NBIO v6.1 driver over to new SOC15 macros
  drm/amd/amdgpu: Port UVD 7.0 over to new SOC15 macros
  drm/amd/amdgpu: Port MMHUB over to new SOC15 macros
  drm/amd/amdgpu: Cleanup gfxhub read-modify-write patterns
  drm/amd/amdgpu: Port GFXHUB over to new SOC15 macros
  drm/amd/amdgpu: Add offset variant to SOC15 macros
  drm/amd/powerplay: add avfs control for Vega10
  drm/amdgpu: add virtual display support for raven
  drm/amdgpu/gfx9: fix compute ring doorbell index
  drm/amd/amdgpu: Rename KIQ ring to avoid spaces
  drm/amd/amdgpu: gfx9 tidy ups (v2)
  drm/amdgpu: add contiguous flag in ucode bo create
  drm/amdgpu: fix missed gpu info firmware when cache firmware during S3
  drm/amdgpu: export test ib debugfs interface
  ...

1 files changed, 60 insertions, 61 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 6b2034533f68..37a499ab30eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -964,62 +964,62 @@ static bool cik_read_bios_from_rom(struct amdgpu_device *adev,
 }
 
 static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = {
-        {mmGRBM_STATUS, false},
-        {mmGB_ADDR_CONFIG, false},
-        {mmMC_ARB_RAMCFG, false},
-        {mmGB_TILE_MODE0, false},
-        {mmGB_TILE_MODE1, false},
-        {mmGB_TILE_MODE2, false},
-        {mmGB_TILE_MODE3, false},
-        {mmGB_TILE_MODE4, false},
-        {mmGB_TILE_MODE5, false},
-        {mmGB_TILE_MODE6, false},
-        {mmGB_TILE_MODE7, false},
-        {mmGB_TILE_MODE8, false},
-        {mmGB_TILE_MODE9, false},
-        {mmGB_TILE_MODE10, false},
-        {mmGB_TILE_MODE11, false},
-        {mmGB_TILE_MODE12, false},
-        {mmGB_TILE_MODE13, false},
-        {mmGB_TILE_MODE14, false},
-        {mmGB_TILE_MODE15, false},
-        {mmGB_TILE_MODE16, false},
-        {mmGB_TILE_MODE17, false},
-        {mmGB_TILE_MODE18, false},
-        {mmGB_TILE_MODE19, false},
-        {mmGB_TILE_MODE20, false},
-        {mmGB_TILE_MODE21, false},
-        {mmGB_TILE_MODE22, false},
-        {mmGB_TILE_MODE23, false},
-        {mmGB_TILE_MODE24, false},
-        {mmGB_TILE_MODE25, false},
-        {mmGB_TILE_MODE26, false},
-        {mmGB_TILE_MODE27, false},
-        {mmGB_TILE_MODE28, false},
-        {mmGB_TILE_MODE29, false},
-        {mmGB_TILE_MODE30, false},
-        {mmGB_TILE_MODE31, false},
-        {mmGB_MACROTILE_MODE0, false},
-        {mmGB_MACROTILE_MODE1, false},
-        {mmGB_MACROTILE_MODE2, false},
-        {mmGB_MACROTILE_MODE3, false},
-        {mmGB_MACROTILE_MODE4, false},
-        {mmGB_MACROTILE_MODE5, false},
-        {mmGB_MACROTILE_MODE6, false},
-        {mmGB_MACROTILE_MODE7, false},
-        {mmGB_MACROTILE_MODE8, false},
-        {mmGB_MACROTILE_MODE9, false},
-        {mmGB_MACROTILE_MODE10, false},
-        {mmGB_MACROTILE_MODE11, false},
-        {mmGB_MACROTILE_MODE12, false},
-        {mmGB_MACROTILE_MODE13, false},
-        {mmGB_MACROTILE_MODE14, false},
-        {mmGB_MACROTILE_MODE15, false},
-        {mmCC_RB_BACKEND_DISABLE, false, true},
-        {mmGC_USER_RB_BACKEND_DISABLE, false, true},
-        {mmGB_BACKEND_MAP, false, false},
-        {mmPA_SC_RASTER_CONFIG, false, true},
-        {mmPA_SC_RASTER_CONFIG_1, false, true},
+        {mmGRBM_STATUS},
+        {mmGB_ADDR_CONFIG},
+        {mmMC_ARB_RAMCFG},
+        {mmGB_TILE_MODE0},
+        {mmGB_TILE_MODE1},
+        {mmGB_TILE_MODE2},
+        {mmGB_TILE_MODE3},
+        {mmGB_TILE_MODE4},
+        {mmGB_TILE_MODE5},
+        {mmGB_TILE_MODE6},
+        {mmGB_TILE_MODE7},
+        {mmGB_TILE_MODE8},
+        {mmGB_TILE_MODE9},
+        {mmGB_TILE_MODE10},
+        {mmGB_TILE_MODE11},
+        {mmGB_TILE_MODE12},
+        {mmGB_TILE_MODE13},
+        {mmGB_TILE_MODE14},
+        {mmGB_TILE_MODE15},
+        {mmGB_TILE_MODE16},
+        {mmGB_TILE_MODE17},
+        {mmGB_TILE_MODE18},
+        {mmGB_TILE_MODE19},
+        {mmGB_TILE_MODE20},
+        {mmGB_TILE_MODE21},
+        {mmGB_TILE_MODE22},
+        {mmGB_TILE_MODE23},
+        {mmGB_TILE_MODE24},
+        {mmGB_TILE_MODE25},
+        {mmGB_TILE_MODE26},
+        {mmGB_TILE_MODE27},
+        {mmGB_TILE_MODE28},
+        {mmGB_TILE_MODE29},
+        {mmGB_TILE_MODE30},
+        {mmGB_TILE_MODE31},
+        {mmGB_MACROTILE_MODE0},
+        {mmGB_MACROTILE_MODE1},
+        {mmGB_MACROTILE_MODE2},
+        {mmGB_MACROTILE_MODE3},
+        {mmGB_MACROTILE_MODE4},
+        {mmGB_MACROTILE_MODE5},
+        {mmGB_MACROTILE_MODE6},
+        {mmGB_MACROTILE_MODE7},
+        {mmGB_MACROTILE_MODE8},
+        {mmGB_MACROTILE_MODE9},
+        {mmGB_MACROTILE_MODE10},
+        {mmGB_MACROTILE_MODE11},
+        {mmGB_MACROTILE_MODE12},
+        {mmGB_MACROTILE_MODE13},
+        {mmGB_MACROTILE_MODE14},
+        {mmGB_MACROTILE_MODE15},
+        {mmCC_RB_BACKEND_DISABLE, true},
+        {mmGC_USER_RB_BACKEND_DISABLE, true},
+        {mmGB_BACKEND_MAP, false},
+        {mmPA_SC_RASTER_CONFIG, true},
+        {mmPA_SC_RASTER_CONFIG_1, true},
 };
 
 static uint32_t cik_read_indexed_register(struct amdgpu_device *adev,
@@ -1050,11 +1050,10 @@ static int cik_read_register(struct amdgpu_device *adev, u32 se_num,
                 if (reg_offset != cik_allowed_read_registers[i].reg_offset)
                         continue;
 
-                if (!cik_allowed_read_registers[i].untouched)
-                        *value = cik_allowed_read_registers[i].grbm_indexed ?
-                                 cik_read_indexed_register(adev, se_num,
-                                                           sh_num, reg_offset) :
-                                 RREG32(reg_offset);
+                *value = cik_allowed_read_registers[i].grbm_indexed ?
+                         cik_read_indexed_register(adev, se_num,
+                                                   sh_num, reg_offset) :
+                         RREG32(reg_offset);
                 return 0;
         }
         return -EINVAL;