diff options
author | Dave Airlie <airlied@redhat.com> | 2016-03-16 18:25:04 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2016-03-16 18:25:04 -0400 |
commit | 9f443bf53b5699835e0132d62d1e6c99a1eaeee8 (patch) | |
tree | 482b1f57019446cc866a0fc8e87bd4b0b0119775 /drivers/gpu/drm/amd/amdgpu/ci_dpm.c | |
parent | 70a09f36d02584fe0025fa14a5cbf276240b2fd4 (diff) | |
parent | 00b7c4ff7d482d287a591f047e0963d494569b46 (diff) |
Merge branch 'drm-next-4.6' of git://people.freedesktop.org/~agd5f/linux into drm-next
A few more fixes and cleanups for 4.6:
- DCE code cleanups
- HDP flush/invalidation fixes
- GPUVM fixes
- switch to drm_vblank_[on|off]
- PX fixes
- misc bug fixes
* 'drm-next-4.6' of git://people.freedesktop.org/~agd5f/linux: (50 commits)
drm/amdgpu: split pipeline sync out of SDMA vm_flush() as well
drm/amdgpu: Revert "add mutex for ba_va->valids/invalids"
drm/amdgpu: Revert "add lock for interval tree in vm"
drm/amdgpu: Revert "add spin lock to protect freed list in vm (v3)"
drm/amdgpu: reserve the PD during unmap and remove
drm/amdgpu: Fix two bugs in amdgpu_vm_bo_split_mapping
drm/radeon: Don't drop DP 2.7 Ghz link setup on some cards.
MAINTAINERS: update radeon entry to include amdgpu as well
drm/amdgpu: disable runtime pm on PX laptops without dGPU power control
drm/radeon: disable runtime pm on PX laptops without dGPU power control
drm/amd/amdgpu: Fix indentation in do_set_base() (DCEv8)
drm/amd/amdgpu: make afmt_init cleanup if alloc fails (DCEv8)
drm/amd/amdgpu: Move config init flag to bottom of sw_init (DCEv8)
drm/amd/amdgpu: Don't proceed into audio_fini if audio is disabled (DCEv8)
drm/amd/amdgpu: Fix identation in do_set_base() (DCEv10)
drm/amd/amdgpu: Make afmt_init cleanup if alloc fails (DCEv10)
drm/amd/amdgpu: Move initialized flag to bottom of sw_init (DCEv10)
drm/amd/amdgpu: Don't proceed in audio_fini if disabled (DCEv10)
drm/amd/amdgpu: Fix indentation in dce_v11_0_crtc_do_set_base()
drm/amd/amdgpu: Make afmt_init() cleanup if alloc fails (DCEv11)
...
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/ci_dpm.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 49 |
1 files changed, 3 insertions, 46 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index 474ca02b0949..1f9109d3348b 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c | |||
@@ -3017,7 +3017,6 @@ static int ci_populate_single_memory_level(struct amdgpu_device *adev, | |||
3017 | &memory_level->MinVddcPhases); | 3017 | &memory_level->MinVddcPhases); |
3018 | 3018 | ||
3019 | memory_level->EnabledForThrottle = 1; | 3019 | memory_level->EnabledForThrottle = 1; |
3020 | memory_level->EnabledForActivity = 1; | ||
3021 | memory_level->UpH = 0; | 3020 | memory_level->UpH = 0; |
3022 | memory_level->DownH = 100; | 3021 | memory_level->DownH = 100; |
3023 | memory_level->VoltageDownH = 0; | 3022 | memory_level->VoltageDownH = 0; |
@@ -3376,7 +3375,6 @@ static int ci_populate_single_graphic_level(struct amdgpu_device *adev, | |||
3376 | graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2); | 3375 | graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2); |
3377 | graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm); | 3376 | graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm); |
3378 | graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1); | 3377 | graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1); |
3379 | graphic_level->EnabledForActivity = 1; | ||
3380 | 3378 | ||
3381 | return 0; | 3379 | return 0; |
3382 | } | 3380 | } |
@@ -3407,6 +3405,7 @@ static int ci_populate_all_graphic_levels(struct amdgpu_device *adev) | |||
3407 | pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = | 3405 | pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = |
3408 | PPSMC_DISPLAY_WATERMARK_HIGH; | 3406 | PPSMC_DISPLAY_WATERMARK_HIGH; |
3409 | } | 3407 | } |
3408 | pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; | ||
3410 | 3409 | ||
3411 | pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; | 3410 | pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; |
3412 | pi->dpm_level_enable_mask.sclk_dpm_enable_mask = | 3411 | pi->dpm_level_enable_mask.sclk_dpm_enable_mask = |
@@ -3450,6 +3449,8 @@ static int ci_populate_all_memory_levels(struct amdgpu_device *adev) | |||
3450 | return ret; | 3449 | return ret; |
3451 | } | 3450 | } |
3452 | 3451 | ||
3452 | pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; | ||
3453 | |||
3453 | if ((dpm_table->mclk_table.count >= 2) && | 3454 | if ((dpm_table->mclk_table.count >= 2) && |
3454 | ((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) { | 3455 | ((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) { |
3455 | pi->smc_state_table.MemoryLevel[1].MinVddc = | 3456 | pi->smc_state_table.MemoryLevel[1].MinVddc = |
@@ -4381,26 +4382,6 @@ static int ci_dpm_force_performance_level(struct amdgpu_device *adev, | |||
4381 | } | 4382 | } |
4382 | } | 4383 | } |
4383 | } | 4384 | } |
4384 | if ((!pi->pcie_dpm_key_disabled) && | ||
4385 | pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { | ||
4386 | levels = 0; | ||
4387 | tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; | ||
4388 | while (tmp >>= 1) | ||
4389 | levels++; | ||
4390 | if (levels) { | ||
4391 | ret = ci_dpm_force_state_pcie(adev, level); | ||
4392 | if (ret) | ||
4393 | return ret; | ||
4394 | for (i = 0; i < adev->usec_timeout; i++) { | ||
4395 | tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) & | ||
4396 | TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >> | ||
4397 | TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT; | ||
4398 | if (tmp == levels) | ||
4399 | break; | ||
4400 | udelay(1); | ||
4401 | } | ||
4402 | } | ||
4403 | } | ||
4404 | } else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) { | 4385 | } else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) { |
4405 | if ((!pi->sclk_dpm_key_disabled) && | 4386 | if ((!pi->sclk_dpm_key_disabled) && |
4406 | pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { | 4387 | pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { |
@@ -5395,30 +5376,6 @@ static int ci_dpm_enable(struct amdgpu_device *adev) | |||
5395 | 5376 | ||
5396 | ci_update_current_ps(adev, boot_ps); | 5377 | ci_update_current_ps(adev, boot_ps); |
5397 | 5378 | ||
5398 | if (adev->irq.installed && | ||
5399 | amdgpu_is_internal_thermal_sensor(adev->pm.int_thermal_type)) { | ||
5400 | #if 0 | ||
5401 | PPSMC_Result result; | ||
5402 | #endif | ||
5403 | ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN, | ||
5404 | CISLANDS_TEMP_RANGE_MAX); | ||
5405 | if (ret) { | ||
5406 | DRM_ERROR("ci_thermal_set_temperature_range failed\n"); | ||
5407 | return ret; | ||
5408 | } | ||
5409 | amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, | ||
5410 | AMDGPU_THERMAL_IRQ_LOW_TO_HIGH); | ||
5411 | amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, | ||
5412 | AMDGPU_THERMAL_IRQ_HIGH_TO_LOW); | ||
5413 | |||
5414 | #if 0 | ||
5415 | result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); | ||
5416 | |||
5417 | if (result != PPSMC_Result_OK) | ||
5418 | DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); | ||
5419 | #endif | ||
5420 | } | ||
5421 | |||
5422 | return 0; | 5379 | return 0; |
5423 | } | 5380 | } |
5424 | 5381 | ||