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authorRex Zhu <Rex.Zhu@amd.com>2016-01-06 04:08:46 -0500
committerAlex Deucher <alexander.deucher@amd.com>2016-01-08 15:39:24 -0500
commit9354573d76f599e05a34e0b468ffce681769115f (patch)
tree64eae4dbfabdb15cc091726ae7448c569312b466 /drivers/gpu/drm/amd/amdgpu/ci_dpm.c
parente0b71a7eff644ca256aee6478bf220ba0a835bed (diff)
drm/amdgpu: Show gpu load when display gpu performance for Ci.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/ci_dpm.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/ci_dpm.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 57a2e347f04d..8b4731d4e10e 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -1395,7 +1395,6 @@ static void ci_thermal_stop_thermal_controller(struct amdgpu_device *adev)
1395 ci_fan_ctrl_set_default_mode(adev); 1395 ci_fan_ctrl_set_default_mode(adev);
1396} 1396}
1397 1397
1398#if 0
1399static int ci_read_smc_soft_register(struct amdgpu_device *adev, 1398static int ci_read_smc_soft_register(struct amdgpu_device *adev,
1400 u16 reg_offset, u32 *value) 1399 u16 reg_offset, u32 *value)
1401{ 1400{
@@ -1405,7 +1404,6 @@ static int ci_read_smc_soft_register(struct amdgpu_device *adev,
1405 pi->soft_regs_start + reg_offset, 1404 pi->soft_regs_start + reg_offset,
1406 value, pi->sram_end); 1405 value, pi->sram_end);
1407} 1406}
1408#endif
1409 1407
1410static int ci_write_smc_soft_register(struct amdgpu_device *adev, 1408static int ci_write_smc_soft_register(struct amdgpu_device *adev,
1411 u16 reg_offset, u32 value) 1409 u16 reg_offset, u32 value)
@@ -6084,11 +6082,23 @@ ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
6084 struct amdgpu_ps *rps = &pi->current_rps; 6082 struct amdgpu_ps *rps = &pi->current_rps;
6085 u32 sclk = ci_get_average_sclk_freq(adev); 6083 u32 sclk = ci_get_average_sclk_freq(adev);
6086 u32 mclk = ci_get_average_mclk_freq(adev); 6084 u32 mclk = ci_get_average_mclk_freq(adev);
6085 u32 activity_percent = 50;
6086 int ret;
6087
6088 ret = ci_read_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, AverageGraphicsA),
6089 &activity_percent);
6090
6091 if (ret == 0) {
6092 activity_percent += 0x80;
6093 activity_percent >>= 8;
6094 activity_percent = activity_percent > 100 ? 100 : activity_percent;
6095 }
6087 6096
6088 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis"); 6097 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");
6089 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis"); 6098 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
6090 seq_printf(m, "power level avg sclk: %u mclk: %u\n", 6099 seq_printf(m, "power level avg sclk: %u mclk: %u\n",
6091 sclk, mclk); 6100 sclk, mclk);
6101 seq_printf(m, "GPU load: %u %%\n", activity_percent);
6092} 6102}
6093 6103
6094static void ci_dpm_print_power_state(struct amdgpu_device *adev, 6104static void ci_dpm_print_power_state(struct amdgpu_device *adev,