drm/amdgpu: add vram_type and vram_bit_width for interface query (v2)

Track the type of vram on the board and provide a query for it.
User mode drivers and tools want this information for determining
bandwidth information and form informational purposes.

v2: fix build when CI support is not enabled

Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>

1 files changed, 6 insertions, 6 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index b1a4fbc22e69..82e8d0730517 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -891,7 +891,7 @@ static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
 static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev)
 {
         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
-        u32 switch_limit = adev->mc.is_gddr5 ? 450 : 300;
+        u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300;
 
         if (vblank_time < switch_limit)
                 return true;
@@ -2920,7 +2920,7 @@ static int ci_calculate_mclk_params(struct amdgpu_device *adev,
         mpll_ad_func_cntl &= ~MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK;
         mpll_ad_func_cntl |= (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
 
-        if (adev->mc.is_gddr5) {
+        if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
                 mpll_dq_func_cntl &= ~(MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK |
                                 MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK);
                 mpll_dq_func_cntl |= (mpll_param.yclk_sel << MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT) |
@@ -3043,7 +3043,7 @@ static int ci_populate_single_memory_level(struct amdgpu_device *adev,
             (memory_clock <= pi->mclk_strobe_mode_threshold))
                 memory_level->StrobeEnable = 1;
 
-        if (adev->mc.is_gddr5) {
+        if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
                 memory_level->StrobeRatio =
                         ci_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
                 if (pi->mclk_edc_enable_threshold &&
@@ -3681,7 +3681,7 @@ static int ci_init_smc_table(struct amdgpu_device *adev)
         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
 
-        if (adev->mc.is_gddr5)
+        if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
 
         if (ulv->supported) {
@@ -4498,14 +4498,14 @@ static int ci_set_mc_special_registers(struct amdgpu_device *adev,
                         for (k = 0; k < table->num_entries; k++) {
                                 table->mc_reg_table_entry[k].mc_data[j] =
                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
-                                if (!adev->mc.is_gddr5)
+                                if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
                         }
                         j++;
                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
                                 return -EINVAL;
 
-                        if (!adev->mc.is_gddr5) {
+                        if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
                                 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
                                 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
                                 for (k = 0; k < table->num_entries; k++) {