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authorTom St Denis <tom.stdenis@amd.com>2016-03-28 08:21:52 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-05-04 20:30:06 -0400
commit16a7989ac62a4d491d44a295577a7e75b7e3b0bb (patch)
treeeddfbeec7e6ad3f51b271b4c31340d5286797b93 /drivers/gpu/drm/amd/amdgpu/ci_dpm.c
parenta72d5604ead32d282fefbc018ca63a3bf878e2c2 (diff)
drm/amd/amdgpu: Drop print_status callbacks.
First patch in series to move to user mode debug tools we're removing the print_status callbacks. These functions were unused at the moment anyway. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/ci_dpm.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/ci_dpm.c210
1 files changed, 0 insertions, 210 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 1f9109d3348b..90f83b21b38c 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -6309,215 +6309,6 @@ static int ci_dpm_wait_for_idle(void *handle)
6309 return 0; 6309 return 0;
6310} 6310}
6311 6311
6312static void ci_dpm_print_status(void *handle)
6313{
6314 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6315
6316 dev_info(adev->dev, "CIK DPM registers\n");
6317 dev_info(adev->dev, " BIOS_SCRATCH_4=0x%08X\n",
6318 RREG32(mmBIOS_SCRATCH_4));
6319 dev_info(adev->dev, " MC_ARB_DRAM_TIMING=0x%08X\n",
6320 RREG32(mmMC_ARB_DRAM_TIMING));
6321 dev_info(adev->dev, " MC_ARB_DRAM_TIMING2=0x%08X\n",
6322 RREG32(mmMC_ARB_DRAM_TIMING2));
6323 dev_info(adev->dev, " MC_ARB_BURST_TIME=0x%08X\n",
6324 RREG32(mmMC_ARB_BURST_TIME));
6325 dev_info(adev->dev, " MC_ARB_DRAM_TIMING_1=0x%08X\n",
6326 RREG32(mmMC_ARB_DRAM_TIMING_1));
6327 dev_info(adev->dev, " MC_ARB_DRAM_TIMING2_1=0x%08X\n",
6328 RREG32(mmMC_ARB_DRAM_TIMING2_1));
6329 dev_info(adev->dev, " MC_CG_CONFIG=0x%08X\n",
6330 RREG32(mmMC_CG_CONFIG));
6331 dev_info(adev->dev, " MC_ARB_CG=0x%08X\n",
6332 RREG32(mmMC_ARB_CG));
6333 dev_info(adev->dev, " DIDT_SQ_CTRL0=0x%08X\n",
6334 RREG32_DIDT(ixDIDT_SQ_CTRL0));
6335 dev_info(adev->dev, " DIDT_DB_CTRL0=0x%08X\n",
6336 RREG32_DIDT(ixDIDT_DB_CTRL0));
6337 dev_info(adev->dev, " DIDT_TD_CTRL0=0x%08X\n",
6338 RREG32_DIDT(ixDIDT_TD_CTRL0));
6339 dev_info(adev->dev, " DIDT_TCP_CTRL0=0x%08X\n",
6340 RREG32_DIDT(ixDIDT_TCP_CTRL0));
6341 dev_info(adev->dev, " CG_THERMAL_INT=0x%08X\n",
6342 RREG32_SMC(ixCG_THERMAL_INT));
6343 dev_info(adev->dev, " CG_THERMAL_CTRL=0x%08X\n",
6344 RREG32_SMC(ixCG_THERMAL_CTRL));
6345 dev_info(adev->dev, " GENERAL_PWRMGT=0x%08X\n",
6346 RREG32_SMC(ixGENERAL_PWRMGT));
6347 dev_info(adev->dev, " MC_SEQ_CNTL_3=0x%08X\n",
6348 RREG32(mmMC_SEQ_CNTL_3));
6349 dev_info(adev->dev, " LCAC_MC0_CNTL=0x%08X\n",
6350 RREG32_SMC(ixLCAC_MC0_CNTL));
6351 dev_info(adev->dev, " LCAC_MC1_CNTL=0x%08X\n",
6352 RREG32_SMC(ixLCAC_MC1_CNTL));
6353 dev_info(adev->dev, " LCAC_CPL_CNTL=0x%08X\n",
6354 RREG32_SMC(ixLCAC_CPL_CNTL));
6355 dev_info(adev->dev, " SCLK_PWRMGT_CNTL=0x%08X\n",
6356 RREG32_SMC(ixSCLK_PWRMGT_CNTL));
6357 dev_info(adev->dev, " BIF_LNCNT_RESET=0x%08X\n",
6358 RREG32(mmBIF_LNCNT_RESET));
6359 dev_info(adev->dev, " FIRMWARE_FLAGS=0x%08X\n",
6360 RREG32_SMC(ixFIRMWARE_FLAGS));
6361 dev_info(adev->dev, " CG_SPLL_FUNC_CNTL=0x%08X\n",
6362 RREG32_SMC(ixCG_SPLL_FUNC_CNTL));
6363 dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_2=0x%08X\n",
6364 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2));
6365 dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_3=0x%08X\n",
6366 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3));
6367 dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_4=0x%08X\n",
6368 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4));
6369 dev_info(adev->dev, " CG_SPLL_SPREAD_SPECTRUM=0x%08X\n",
6370 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM));
6371 dev_info(adev->dev, " CG_SPLL_SPREAD_SPECTRUM_2=0x%08X\n",
6372 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2));
6373 dev_info(adev->dev, " DLL_CNTL=0x%08X\n",
6374 RREG32(mmDLL_CNTL));
6375 dev_info(adev->dev, " MCLK_PWRMGT_CNTL=0x%08X\n",
6376 RREG32(mmMCLK_PWRMGT_CNTL));
6377 dev_info(adev->dev, " MPLL_AD_FUNC_CNTL=0x%08X\n",
6378 RREG32(mmMPLL_AD_FUNC_CNTL));
6379 dev_info(adev->dev, " MPLL_DQ_FUNC_CNTL=0x%08X\n",
6380 RREG32(mmMPLL_DQ_FUNC_CNTL));
6381 dev_info(adev->dev, " MPLL_FUNC_CNTL=0x%08X\n",
6382 RREG32(mmMPLL_FUNC_CNTL));
6383 dev_info(adev->dev, " MPLL_FUNC_CNTL_1=0x%08X\n",
6384 RREG32(mmMPLL_FUNC_CNTL_1));
6385 dev_info(adev->dev, " MPLL_FUNC_CNTL_2=0x%08X\n",
6386 RREG32(mmMPLL_FUNC_CNTL_2));
6387 dev_info(adev->dev, " MPLL_SS1=0x%08X\n",
6388 RREG32(mmMPLL_SS1));
6389 dev_info(adev->dev, " MPLL_SS2=0x%08X\n",
6390 RREG32(mmMPLL_SS2));
6391 dev_info(adev->dev, " CG_DISPLAY_GAP_CNTL=0x%08X\n",
6392 RREG32_SMC(ixCG_DISPLAY_GAP_CNTL));
6393 dev_info(adev->dev, " CG_DISPLAY_GAP_CNTL2=0x%08X\n",
6394 RREG32_SMC(ixCG_DISPLAY_GAP_CNTL2));
6395 dev_info(adev->dev, " CG_STATIC_SCREEN_PARAMETER=0x%08X\n",
6396 RREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER));
6397 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_0=0x%08X\n",
6398 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_0));
6399 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_1=0x%08X\n",
6400 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_1));
6401 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_2=0x%08X\n",
6402 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_2));
6403 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_3=0x%08X\n",
6404 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_3));
6405 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_4=0x%08X\n",
6406 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_4));
6407 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_5=0x%08X\n",
6408 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_5));
6409 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_6=0x%08X\n",
6410 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_6));
6411 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_7=0x%08X\n",
6412 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_7));
6413 dev_info(adev->dev, " RCU_UC_EVENTS=0x%08X\n",
6414 RREG32_SMC(ixRCU_UC_EVENTS));
6415 dev_info(adev->dev, " DPM_TABLE_475=0x%08X\n",
6416 RREG32_SMC(ixDPM_TABLE_475));
6417 dev_info(adev->dev, " MC_SEQ_RAS_TIMING_LP=0x%08X\n",
6418 RREG32(mmMC_SEQ_RAS_TIMING_LP));
6419 dev_info(adev->dev, " MC_SEQ_RAS_TIMING=0x%08X\n",
6420 RREG32(mmMC_SEQ_RAS_TIMING));
6421 dev_info(adev->dev, " MC_SEQ_CAS_TIMING_LP=0x%08X\n",
6422 RREG32(mmMC_SEQ_CAS_TIMING_LP));
6423 dev_info(adev->dev, " MC_SEQ_CAS_TIMING=0x%08X\n",
6424 RREG32(mmMC_SEQ_CAS_TIMING));
6425 dev_info(adev->dev, " MC_SEQ_DLL_STBY_LP=0x%08X\n",
6426 RREG32(mmMC_SEQ_DLL_STBY_LP));
6427 dev_info(adev->dev, " MC_SEQ_DLL_STBY=0x%08X\n",
6428 RREG32(mmMC_SEQ_DLL_STBY));
6429 dev_info(adev->dev, " MC_SEQ_G5PDX_CMD0_LP=0x%08X\n",
6430 RREG32(mmMC_SEQ_G5PDX_CMD0_LP));
6431 dev_info(adev->dev, " MC_SEQ_G5PDX_CMD0=0x%08X\n",
6432 RREG32(mmMC_SEQ_G5PDX_CMD0));
6433 dev_info(adev->dev, " MC_SEQ_G5PDX_CMD1_LP=0x%08X\n",
6434 RREG32(mmMC_SEQ_G5PDX_CMD1_LP));
6435 dev_info(adev->dev, " MC_SEQ_G5PDX_CMD1=0x%08X\n",
6436 RREG32(mmMC_SEQ_G5PDX_CMD1));
6437 dev_info(adev->dev, " MC_SEQ_G5PDX_CTRL_LP=0x%08X\n",
6438 RREG32(mmMC_SEQ_G5PDX_CTRL_LP));
6439 dev_info(adev->dev, " MC_SEQ_G5PDX_CTRL=0x%08X\n",
6440 RREG32(mmMC_SEQ_G5PDX_CTRL));
6441 dev_info(adev->dev, " MC_SEQ_PMG_DVS_CMD_LP=0x%08X\n",
6442 RREG32(mmMC_SEQ_PMG_DVS_CMD_LP));
6443 dev_info(adev->dev, " MC_SEQ_PMG_DVS_CMD=0x%08X\n",
6444 RREG32(mmMC_SEQ_PMG_DVS_CMD));
6445 dev_info(adev->dev, " MC_SEQ_PMG_DVS_CTL_LP=0x%08X\n",
6446 RREG32(mmMC_SEQ_PMG_DVS_CTL_LP));
6447 dev_info(adev->dev, " MC_SEQ_PMG_DVS_CTL=0x%08X\n",
6448 RREG32(mmMC_SEQ_PMG_DVS_CTL));
6449 dev_info(adev->dev, " MC_SEQ_MISC_TIMING_LP=0x%08X\n",
6450 RREG32(mmMC_SEQ_MISC_TIMING_LP));
6451 dev_info(adev->dev, " MC_SEQ_MISC_TIMING=0x%08X\n",
6452 RREG32(mmMC_SEQ_MISC_TIMING));
6453 dev_info(adev->dev, " MC_SEQ_MISC_TIMING2_LP=0x%08X\n",
6454 RREG32(mmMC_SEQ_MISC_TIMING2_LP));
6455 dev_info(adev->dev, " MC_SEQ_MISC_TIMING2=0x%08X\n",
6456 RREG32(mmMC_SEQ_MISC_TIMING2));
6457 dev_info(adev->dev, " MC_SEQ_PMG_CMD_EMRS_LP=0x%08X\n",
6458 RREG32(mmMC_SEQ_PMG_CMD_EMRS_LP));
6459 dev_info(adev->dev, " MC_PMG_CMD_EMRS=0x%08X\n",
6460 RREG32(mmMC_PMG_CMD_EMRS));
6461 dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS_LP=0x%08X\n",
6462 RREG32(mmMC_SEQ_PMG_CMD_MRS_LP));
6463 dev_info(adev->dev, " MC_PMG_CMD_MRS=0x%08X\n",
6464 RREG32(mmMC_PMG_CMD_MRS));
6465 dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS1_LP=0x%08X\n",
6466 RREG32(mmMC_SEQ_PMG_CMD_MRS1_LP));
6467 dev_info(adev->dev, " MC_PMG_CMD_MRS1=0x%08X\n",
6468 RREG32(mmMC_PMG_CMD_MRS1));
6469 dev_info(adev->dev, " MC_SEQ_WR_CTL_D0_LP=0x%08X\n",
6470 RREG32(mmMC_SEQ_WR_CTL_D0_LP));
6471 dev_info(adev->dev, " MC_SEQ_WR_CTL_D0=0x%08X\n",
6472 RREG32(mmMC_SEQ_WR_CTL_D0));
6473 dev_info(adev->dev, " MC_SEQ_WR_CTL_D1_LP=0x%08X\n",
6474 RREG32(mmMC_SEQ_WR_CTL_D1_LP));
6475 dev_info(adev->dev, " MC_SEQ_WR_CTL_D1=0x%08X\n",
6476 RREG32(mmMC_SEQ_WR_CTL_D1));
6477 dev_info(adev->dev, " MC_SEQ_RD_CTL_D0_LP=0x%08X\n",
6478 RREG32(mmMC_SEQ_RD_CTL_D0_LP));
6479 dev_info(adev->dev, " MC_SEQ_RD_CTL_D0=0x%08X\n",
6480 RREG32(mmMC_SEQ_RD_CTL_D0));
6481 dev_info(adev->dev, " MC_SEQ_RD_CTL_D1_LP=0x%08X\n",
6482 RREG32(mmMC_SEQ_RD_CTL_D1_LP));
6483 dev_info(adev->dev, " MC_SEQ_RD_CTL_D1=0x%08X\n",
6484 RREG32(mmMC_SEQ_RD_CTL_D1));
6485 dev_info(adev->dev, " MC_SEQ_PMG_TIMING_LP=0x%08X\n",
6486 RREG32(mmMC_SEQ_PMG_TIMING_LP));
6487 dev_info(adev->dev, " MC_SEQ_PMG_TIMING=0x%08X\n",
6488 RREG32(mmMC_SEQ_PMG_TIMING));
6489 dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS2_LP=0x%08X\n",
6490 RREG32(mmMC_SEQ_PMG_CMD_MRS2_LP));
6491 dev_info(adev->dev, " MC_PMG_CMD_MRS2=0x%08X\n",
6492 RREG32(mmMC_PMG_CMD_MRS2));
6493 dev_info(adev->dev, " MC_SEQ_WR_CTL_2_LP=0x%08X\n",
6494 RREG32(mmMC_SEQ_WR_CTL_2_LP));
6495 dev_info(adev->dev, " MC_SEQ_WR_CTL_2=0x%08X\n",
6496 RREG32(mmMC_SEQ_WR_CTL_2));
6497 dev_info(adev->dev, " PCIE_LC_SPEED_CNTL=0x%08X\n",
6498 RREG32_PCIE(ixPCIE_LC_SPEED_CNTL));
6499 dev_info(adev->dev, " PCIE_LC_LINK_WIDTH_CNTL=0x%08X\n",
6500 RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL));
6501 dev_info(adev->dev, " SMC_IND_INDEX_0=0x%08X\n",
6502 RREG32(mmSMC_IND_INDEX_0));
6503 dev_info(adev->dev, " SMC_IND_DATA_0=0x%08X\n",
6504 RREG32(mmSMC_IND_DATA_0));
6505 dev_info(adev->dev, " SMC_IND_ACCESS_CNTL=0x%08X\n",
6506 RREG32(mmSMC_IND_ACCESS_CNTL));
6507 dev_info(adev->dev, " SMC_RESP_0=0x%08X\n",
6508 RREG32(mmSMC_RESP_0));
6509 dev_info(adev->dev, " SMC_MESSAGE_0=0x%08X\n",
6510 RREG32(mmSMC_MESSAGE_0));
6511 dev_info(adev->dev, " SMC_SYSCON_RESET_CNTL=0x%08X\n",
6512 RREG32_SMC(ixSMC_SYSCON_RESET_CNTL));
6513 dev_info(adev->dev, " SMC_SYSCON_CLOCK_CNTL_0=0x%08X\n",
6514 RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0));
6515 dev_info(adev->dev, " SMC_SYSCON_MISC_CNTL=0x%08X\n",
6516 RREG32_SMC(ixSMC_SYSCON_MISC_CNTL));
6517 dev_info(adev->dev, " SMC_PC_C=0x%08X\n",
6518 RREG32_SMC(ixSMC_PC_C));
6519}
6520
6521static int ci_dpm_soft_reset(void *handle) 6312static int ci_dpm_soft_reset(void *handle)
6522{ 6313{
6523 return 0; 6314 return 0;
@@ -6625,7 +6416,6 @@ const struct amd_ip_funcs ci_dpm_ip_funcs = {
6625 .is_idle = ci_dpm_is_idle, 6416 .is_idle = ci_dpm_is_idle,
6626 .wait_for_idle = ci_dpm_wait_for_idle, 6417 .wait_for_idle = ci_dpm_wait_for_idle,
6627 .soft_reset = ci_dpm_soft_reset, 6418 .soft_reset = ci_dpm_soft_reset,
6628 .print_status = ci_dpm_print_status,
6629 .set_clockgating_state = ci_dpm_set_clockgating_state, 6419 .set_clockgating_state = ci_dpm_set_clockgating_state,
6630 .set_powergating_state = ci_dpm_set_powergating_state, 6420 .set_powergating_state = ci_dpm_set_powergating_state,
6631}; 6421};
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 19:57:55 -0400