drm/amd/amdgpu: store fragment_size in vm_manager

adds fragment_size in the vm_manager structure and
implements hardware setup for it.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Roger He <Hongbo.He@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 1 insertions, 5 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index a740b57e9eee..45a276960d02 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -50,11 +50,6 @@ struct amdgpu_bo_list_entry;
 /* PTBs (Page Table Blocks) need to be aligned to 32K */
 #define AMDGPU_VM_PTB_ALIGN_SIZE   32768
 
-/* LOG2 number of continuous pages for the fragment field */
-#define AMDGPU_LOG2_PAGES_PER_FRAG(adev) \
-        ((adev)->asic_type < CHIP_VEGA10 ? 4 : \
-         (adev)->vm_manager.block_size)
-
 #define AMDGPU_PTE_VALID        (1ULL << 0)
 #define AMDGPU_PTE_SYSTEM       (1ULL << 1)
 #define AMDGPU_PTE_SNOOPED      (1ULL << 2)
@@ -200,6 +195,7 @@ struct amdgpu_vm_manager {
         uint32_t                                num_level;
         uint64_t                                vm_size;
         uint32_t                                block_size;
+        uint32_t                                fragment_size;
         /* vram base address for page table entry  */
         u64                                     vram_base_offset;
         /* vm pte handling */