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authorshaoyunl <shaoyun.liu@amd.com>2019-02-22 16:20:38 -0500
committerAlex Deucher <alexander.deucher@amd.com>2019-03-19 16:36:48 -0400
commita690aa0f459eba3e768257a655c82b24d14dcc88 (patch)
tree9c4d90d696a58b0a35ff9e2eae1fa5e9195dd1e5 /drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
parentb1fa8c89556e8d704e9a2e014151c47c64f02e06 (diff)
drm/amdgpu: Enable XGMI mapping for peer device
Adjust vram base offset for XGMI mapping when update the PT entry so the address will fall into correct XGMI aperture for peer device Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c13
1 files changed, 9 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 1b5a2b29c95b..67d638fef1fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1876,6 +1876,7 @@ error_free:
1876 * @vm: requested vm 1876 * @vm: requested vm
1877 * @mapping: mapped range and flags to use for the update 1877 * @mapping: mapped range and flags to use for the update
1878 * @flags: HW flags for the mapping 1878 * @flags: HW flags for the mapping
1879 * @bo_adev: amdgpu_device pointer that bo actually been allocated
1879 * @nodes: array of drm_mm_nodes with the MC addresses 1880 * @nodes: array of drm_mm_nodes with the MC addresses
1880 * @fence: optional resulting fence 1881 * @fence: optional resulting fence
1881 * 1882 *
@@ -1891,6 +1892,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1891 struct amdgpu_vm *vm, 1892 struct amdgpu_vm *vm,
1892 struct amdgpu_bo_va_mapping *mapping, 1893 struct amdgpu_bo_va_mapping *mapping,
1893 uint64_t flags, 1894 uint64_t flags,
1895 struct amdgpu_device *bo_adev,
1894 struct drm_mm_node *nodes, 1896 struct drm_mm_node *nodes,
1895 struct dma_fence **fence) 1897 struct dma_fence **fence)
1896{ 1898{
@@ -1965,7 +1967,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1965 } 1967 }
1966 1968
1967 } else if (flags & AMDGPU_PTE_VALID) { 1969 } else if (flags & AMDGPU_PTE_VALID) {
1968 addr += adev->vm_manager.vram_base_offset; 1970 addr += bo_adev->vm_manager.vram_base_offset;
1969 addr += pfn << PAGE_SHIFT; 1971 addr += pfn << PAGE_SHIFT;
1970 } 1972 }
1971 1973
@@ -2012,6 +2014,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
2012 struct drm_mm_node *nodes; 2014 struct drm_mm_node *nodes;
2013 struct dma_fence *exclusive, **last_update; 2015 struct dma_fence *exclusive, **last_update;
2014 uint64_t flags; 2016 uint64_t flags;
2017 struct amdgpu_device *bo_adev = adev;
2015 int r; 2018 int r;
2016 2019
2017 if (clear || !bo) { 2020 if (clear || !bo) {
@@ -2030,10 +2033,12 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
2030 exclusive = reservation_object_get_excl(bo->tbo.resv); 2033 exclusive = reservation_object_get_excl(bo->tbo.resv);
2031 } 2034 }
2032 2035
2033 if (bo) 2036 if (bo) {
2034 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem); 2037 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
2035 else 2038 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
2039 } else {
2036 flags = 0x0; 2040 flags = 0x0;
2041 }
2037 2042
2038 if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv)) 2043 if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
2039 last_update = &vm->last_update; 2044 last_update = &vm->last_update;
@@ -2050,7 +2055,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
2050 2055
2051 list_for_each_entry(mapping, &bo_va->invalids, list) { 2056 list_for_each_entry(mapping, &bo_va->invalids, list) {
2052 r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm, 2057 r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
2053 mapping, flags, nodes, 2058 mapping, flags, bo_adev, nodes,
2054 last_update); 2059 last_update);
2055 if (r) 2060 if (r)
2056 return r; 2061 return r;