Merge branch 'drm-next-4.3' of git://people.freedesktop.org/~agd5f/linux into drm-next

More fixes for radeon and amdgpu for 4.3:
- Send full DP aux address fixes for radeon and amdgpu
- Fix an HDMI display regression for pre-DCE5 parts
- UVD suspend fixes for amdgpu
- Add an rs480 suspend quirk
- Fix bo reserve handling in amdgpu GEM_OP ioctl
- GPU scheduler fixes
- SDMA optimizations
- MEC fix for Fiji

* 'drm-next-4.3' of git://people.freedesktop.org/~agd5f/linux: (21 commits)
  drm/amdgpu: set MEC doorbell range for Fiji
  drm/amdgpu: implement burst NOP for SDMA
  drm/amdgpu: add insert_nop ring func and default implementation
  drm/amdgpu: add amdgpu_get_sdma_instance helper function
  drm/amdgpu: add AMDGPU_MAX_SDMA_INSTANCES
  drm/amdgpu: add burst_nop flag for sdma
  drm/amdgpu: add count field for the SDMA NOP packet v2
  drm/amdgpu: use PT for VM sync on unmap
  drm/amdgpu: make wait_event uninterruptible in push_job
  drm/amdgpu: fix amdgpu_bo_unreserve order in GEM_OP IOCTL v2
  drm/amdgpu: partially revert "modify amdgpu_fence_wait_any() to amdgpu_fence_wait_multiple()" v2
  Add radeon suspend/resume quirk for HP Compaq dc5750.
  drm/amdgpu: re-work sync_resv
  drm/amdgpu/atom: Send out the full AUX address
  drm/radeon/native: Send out the full AUX address
  drm/radeon/atom: Send out the full AUX address
  drm/amdgpu: use IB for fill_buffer instead of direct command
  drm/amdgpu: stop trying to suspend UVD sessions v2
  drm/amdgpu: add scheduler dependency callback v2
  drm/amdgpu: let the scheduler work more with jobs v2
  ...

1 files changed, 6 insertions, 13 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 83b7ce6f5f72..5848564d3d66 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -627,9 +627,14 @@ static int amdgpu_vm_update_ptes(struct amdgpu_device *adev,
 {
         uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
         uint64_t last_pte = ~0, last_dst = ~0;
+        void *owner = AMDGPU_FENCE_OWNER_VM;
         unsigned count = 0;
         uint64_t addr;
 
+        /* sync to everything on unmapping */
+        if (!(flags & AMDGPU_PTE_VALID))
+                owner = AMDGPU_FENCE_OWNER_UNDEFINED;
+
         /* walk over the address space and update the page tables */
         for (addr = start; addr < end; ) {
                 uint64_t pt_idx = addr >> amdgpu_vm_block_size;
@@ -638,8 +643,7 @@ static int amdgpu_vm_update_ptes(struct amdgpu_device *adev,
                 uint64_t pte;
                 int r;
 
-                amdgpu_sync_resv(adev, &ib->sync, pt->tbo.resv,
-                                 AMDGPU_FENCE_OWNER_VM);
+                amdgpu_sync_resv(adev, &ib->sync, pt->tbo.resv, owner);
                 r = reservation_object_reserve_shared(pt->tbo.resv);
                 if (r)
                         return r;
@@ -790,17 +794,6 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 
         ib->length_dw = 0;
 
-        if (!(flags & AMDGPU_PTE_VALID)) {
-                unsigned i;
-
-                for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
-                        struct amdgpu_fence *f = vm->ids[i].last_id_use;
-                        r = amdgpu_sync_fence(adev, &ib->sync, &f->base);
-                        if (r)
-                                return r;
-                }
-        }
-
         r = amdgpu_vm_update_ptes(adev, vm, ib, mapping->it.start,
                                   mapping->it.last + 1, addr + mapping->offset,
                                   flags, gtt_flags);