drm/amdgpu/vcn:Replace value with defined macro

Replace value with defined macro to make
code more readable

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 7 insertions, 4 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 12a60ecd44b3..a75745904b81 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -309,14 +309,17 @@ static int amdgpu_vcn_pause_dpg_mode(struct amdgpu_device *adev,
                                 /* Restore */
                                 ring = &adev->vcn.ring_jpeg;
                                 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
-                                WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000001L | 0x00000002L);
+                                WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
+                                                        UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
+                                                        UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
                                 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
-                                             lower_32_bits(ring->gpu_addr));
+                                                        lower_32_bits(ring->gpu_addr));
                                 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
-                                             upper_32_bits(ring->gpu_addr));
+                                                        upper_32_bits(ring->gpu_addr));
                                 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr);
                                 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);
-                                WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
+                                WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
+                                                        UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
 
                                 ring = &adev->vcn.ring_dec;
                                 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,