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authorChristian König <christian.koenig@amd.com>2016-07-01 11:43:57 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-07-14 16:46:03 -0400
commit182830a1783ad35f93b9f1a6003a7a48074ed53d (patch)
tree7ea6a6e7abc7a498ee4480ad5e2d1e838c13957a /drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
parent4f399a082866e137cd3c3bdf329f5c7ce1dca5d7 (diff)
drm/amdgpu: cleanup VCE coding style
Fix 80 chars issues and remove some dead code as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c47
1 files changed, 21 insertions, 26 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 875626a2eccb..473eb092149a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -36,7 +36,7 @@
36#include "cikd.h" 36#include "cikd.h"
37 37
38/* 1 second timeout */ 38/* 1 second timeout */
39#define VCE_IDLE_TIMEOUT_MS 1000 39#define VCE_IDLE_TIMEOUT msecs_to_jiffies(1000)
40 40
41/* Firmware Names */ 41/* Firmware Names */
42#ifdef CONFIG_DRM_AMDGPU_CIK 42#ifdef CONFIG_DRM_AMDGPU_CIK
@@ -310,8 +310,7 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work)
310 amdgpu_asic_set_vce_clocks(adev, 0, 0); 310 amdgpu_asic_set_vce_clocks(adev, 0, 0);
311 } 311 }
312 } else { 312 } else {
313 schedule_delayed_work(&adev->vce.idle_work, 313 schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT);
314 msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
315 } 314 }
316} 315}
317 316
@@ -324,17 +323,12 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work)
324 */ 323 */
325static void amdgpu_vce_note_usage(struct amdgpu_device *adev) 324static void amdgpu_vce_note_usage(struct amdgpu_device *adev)
326{ 325{
327 bool streams_changed = false;
328 bool set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work); 326 bool set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
329 set_clocks &= schedule_delayed_work(&adev->vce.idle_work,
330 msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
331 327
332 if (adev->pm.dpm_enabled) { 328 set_clocks &= schedule_delayed_work(&adev->vce.idle_work,
333 /* XXX figure out if the streams changed */ 329 VCE_IDLE_TIMEOUT);
334 streams_changed = false;
335 }
336 330
337 if (set_clocks || streams_changed) { 331 if (set_clocks) {
338 if (adev->pm.dpm_enabled) { 332 if (adev->pm.dpm_enabled) {
339 amdgpu_dpm_enable_vce(adev, true); 333 amdgpu_dpm_enable_vce(adev, true);
340 } else { 334 } else {
@@ -357,6 +351,7 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
357 int i, r; 351 int i, r;
358 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) { 352 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
359 uint32_t handle = atomic_read(&adev->vce.handles[i]); 353 uint32_t handle = atomic_read(&adev->vce.handles[i]);
354
360 if (!handle || adev->vce.filp[i] != filp) 355 if (!handle || adev->vce.filp[i] != filp)
361 continue; 356 continue;
362 357
@@ -648,7 +643,7 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
648 } 643 }
649 644
650 switch (cmd) { 645 switch (cmd) {
651 case 0x00000001: // session 646 case 0x00000001: /* session */
652 handle = amdgpu_get_ib_value(p, ib_idx, idx + 2); 647 handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
653 session_idx = amdgpu_vce_validate_handle(p, handle, 648 session_idx = amdgpu_vce_validate_handle(p, handle,
654 &allocated); 649 &allocated);
@@ -657,12 +652,12 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
657 size = &p->adev->vce.img_size[session_idx]; 652 size = &p->adev->vce.img_size[session_idx];
658 break; 653 break;
659 654
660 case 0x00000002: // task info 655 case 0x00000002: /* task info */
661 fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6); 656 fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
662 bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7); 657 bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
663 break; 658 break;
664 659
665 case 0x01000001: // create 660 case 0x01000001: /* create */
666 created = true; 661 created = true;
667 if (!allocated) { 662 if (!allocated) {
668 DRM_ERROR("Handle already in use!\n"); 663 DRM_ERROR("Handle already in use!\n");
@@ -675,16 +670,16 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
675 8 * 3 / 2; 670 8 * 3 / 2;
676 break; 671 break;
677 672
678 case 0x04000001: // config extension 673 case 0x04000001: /* config extension */
679 case 0x04000002: // pic control 674 case 0x04000002: /* pic control */
680 case 0x04000005: // rate control 675 case 0x04000005: /* rate control */
681 case 0x04000007: // motion estimation 676 case 0x04000007: /* motion estimation */
682 case 0x04000008: // rdo 677 case 0x04000008: /* rdo */
683 case 0x04000009: // vui 678 case 0x04000009: /* vui */
684 case 0x05000002: // auxiliary buffer 679 case 0x05000002: /* auxiliary buffer */
685 break; 680 break;
686 681
687 case 0x03000001: // encode 682 case 0x03000001: /* encode */
688 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9, 683 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9,
689 *size, 0); 684 *size, 0);
690 if (r) 685 if (r)
@@ -696,18 +691,18 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
696 goto out; 691 goto out;
697 break; 692 break;
698 693
699 case 0x02000001: // destroy 694 case 0x02000001: /* destroy */
700 destroyed = true; 695 destroyed = true;
701 break; 696 break;
702 697
703 case 0x05000001: // context buffer 698 case 0x05000001: /* context buffer */
704 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2, 699 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
705 *size * 2, 0); 700 *size * 2, 0);
706 if (r) 701 if (r)
707 goto out; 702 goto out;
708 break; 703 break;
709 704
710 case 0x05000004: // video bitstream buffer 705 case 0x05000004: /* video bitstream buffer */
711 tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4); 706 tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
712 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2, 707 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
713 tmp, bs_idx); 708 tmp, bs_idx);
@@ -715,7 +710,7 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
715 goto out; 710 goto out;
716 break; 711 break;
717 712
718 case 0x05000005: // feedback buffer 713 case 0x05000005: /* feedback buffer */
719 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2, 714 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
720 4096, fb_idx); 715 4096, fb_idx);
721 if (r) 716 if (r)