diff options
author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2017-02-26 15:34:42 -0500 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2017-02-26 15:34:42 -0500 |
commit | 8e22e1b3499a446df48c2b26667ca36c55bf864c (patch) | |
tree | 5329f98b3eb3c95a9dcbab0fa4f9b6e62f0e788d /drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | |
parent | 00d3c14f14d51babd8aeafd5fa734ccf04f5ca3d (diff) | |
parent | 64a577196d66b44e37384bc5c4d78c61f59d5b2a (diff) |
Merge airlied/drm-next into drm-misc-next
Backmerge the main pull request to sync up with all the newly landed
drivers. Otherwise we'll have chaos even before 4.12 started in
earnest.
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 6f62ac473064..6d6ab7f11b4c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | |||
@@ -1113,6 +1113,11 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work) | |||
1113 | amdgpu_dpm_enable_uvd(adev, false); | 1113 | amdgpu_dpm_enable_uvd(adev, false); |
1114 | } else { | 1114 | } else { |
1115 | amdgpu_asic_set_uvd_clocks(adev, 0, 0); | 1115 | amdgpu_asic_set_uvd_clocks(adev, 0, 0); |
1116 | /* shutdown the UVD block */ | ||
1117 | amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, | ||
1118 | AMD_PG_STATE_GATE); | ||
1119 | amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, | ||
1120 | AMD_CG_STATE_GATE); | ||
1116 | } | 1121 | } |
1117 | } else { | 1122 | } else { |
1118 | schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); | 1123 | schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); |
@@ -1129,6 +1134,10 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) | |||
1129 | amdgpu_dpm_enable_uvd(adev, true); | 1134 | amdgpu_dpm_enable_uvd(adev, true); |
1130 | } else { | 1135 | } else { |
1131 | amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); | 1136 | amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); |
1137 | amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, | ||
1138 | AMD_CG_STATE_UNGATE); | ||
1139 | amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, | ||
1140 | AMD_PG_STATE_UNGATE); | ||
1132 | } | 1141 | } |
1133 | } | 1142 | } |
1134 | } | 1143 | } |