Merge tag 'drm-fixes-2018-06-22' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "Just run of the mill fixes,

  core:
   - regression fix in device unplug

  qxl:
   - regression fix for might sleep in cursor handling

  nouveau:
   - regression fix in multi-screen cursor handling

  amdgpu:
   - switch off DC by default on Kaveri and older
   - some minor fixes

  i915:
   - some GEM regression fixes
   - doublescan mode fixes

  sun4i:
   - revert fix for a regression

  sii8620 bridge:
   - misc fixes"

* tag 'drm-fixes-2018-06-22' of git://anongit.freedesktop.org/drm/drm: (28 commits)
  drm/bridge/sii8620: fix display of packed pixel modes in MHL2
  drm/amdgpu: Make amdgpu_vram_mgr_bo_invisible_size always accurate
  drm/amdgpu: Refactor amdgpu_vram_mgr_bo_invisible_size helper
  drm/amdgpu: Update pin_size values before unpinning BO
  drm/amdgpu:All UVD instances share one idle_work handle
  drm/amdgpu: Don't default to DC support for Kaveri and older
  drm/amdgpu: Use kvmalloc_array for allocating VRAM manager nodes array
  drm/amd/pp: Fix uninitialized variable
  drm/i915: Enable provoking vertex fix on Gen9 systems.
  drm/i915: Fix context ban and hang accounting for client
  drm/i915: Turn off g4x DP port in .post_disable()
  drm/i915: Disallow interlaced modes on g4x DP outputs
  drm/i915: Fix PIPESTAT irq ack on i965/g4x
  drm/i915: Allow DBLSCAN user modes with eDP/LVDS/DSI
  drm/i915/execlists: Avoid putting the error pointer
  drm/i915: Apply batch location restrictions before pinning
  drm/nouveau/kms/nv50-: cursors always use core channel vram ctxdma
  Revert "drm/sun4i: Handle DRM_BUS_FLAG_PIXDATA_*EDGE"
  drm/atmel-hlcdc: check stride values in the first plane
  drm/bridge/sii8620: fix HDMI cable connection to dongle
  ...

1 files changed, 7 insertions, 7 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index bcf68f80bbf0..3ff08e326838 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -130,7 +130,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
         unsigned version_major, version_minor, family_id;
         int i, j, r;
 
-        INIT_DELAYED_WORK(&adev->uvd.inst->idle_work, amdgpu_uvd_idle_work_handler);
+        INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
 
         switch (adev->asic_type) {
 #ifdef CONFIG_DRM_AMDGPU_CIK
@@ -314,12 +314,12 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
         void *ptr;
         int i, j;
 
+        cancel_delayed_work_sync(&adev->uvd.idle_work);
+
         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
                 if (adev->uvd.inst[j].vcpu_bo == NULL)
                         continue;
 
-                cancel_delayed_work_sync(&adev->uvd.inst[j].idle_work);
-
                 /* only valid for physical mode */
                 if (adev->asic_type < CHIP_POLARIS10) {
                         for (i = 0; i < adev->uvd.max_handles; ++i)
@@ -1145,7 +1145,7 @@ int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
 {
         struct amdgpu_device *adev =
-                container_of(work, struct amdgpu_device, uvd.inst->idle_work.work);
+                container_of(work, struct amdgpu_device, uvd.idle_work.work);
         unsigned fences = 0, i, j;
 
         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
@@ -1167,7 +1167,7 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
                                                                AMD_CG_STATE_GATE);
                 }
         } else {
-                schedule_delayed_work(&adev->uvd.inst->idle_work, UVD_IDLE_TIMEOUT);
+                schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
         }
 }
 
@@ -1179,7 +1179,7 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
         if (amdgpu_sriov_vf(adev))
                 return;
 
-        set_clocks = !cancel_delayed_work_sync(&adev->uvd.inst->idle_work);
+        set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
         if (set_clocks) {
                 if (adev->pm.dpm_enabled) {
                         amdgpu_dpm_enable_uvd(adev, true);
@@ -1196,7 +1196,7 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring)
 {
         if (!amdgpu_sriov_vf(ring->adev))
-                schedule_delayed_work(&ring->adev->uvd.inst->idle_work, UVD_IDLE_TIMEOUT);
+                schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
 }
 
 /**